@@ -724,6 +724,32 @@ static struct davinci_uart_config uart_config __initdata = {
#define DM646X_EVM_PHY_MASK (0x2)
#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
+/*
+ * The following EDMA channels/slots are not being used by drivers (for
+ * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
+ * reserved for codecs on the DSP side.
+ */
+static const s16 dm646x_dma_rsv_chans[][2] = {
+ /* (offset, number) */
+ { 0, 4},
+ {13, 3},
+ {24, 4},
+ {30, 2},
+ {54, 3},
+ {-1, -1}
+};
+
+static const s16 dm646x_dma_rsv_slots[][2] = {
+ /* (offset, number) */
+ { 0, 4},
+ {13, 3},
+ {24, 4},
+ {30, 2},
+ {54, 3},
+ {128, 384},
+ {-1, -1}
+};
+
static __init void evm_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -735,6 +761,8 @@ static __init void evm_init(void)
platform_device_register(&davinci_nand_device);
+ dm646x_init_edma(dm646x_dma_rsv_chans, dm646x_dma_rsv_slots);
+
if (HAS_ATA)
dm646x_init_ide();
@@ -912,6 +912,15 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
platform_device_register(&vpif_capture_dev);
}
+int __init dm646x_init_edma(const s16 (*rsv_chans)[2],
+ const s16 (*rsv_slots)[2])
+{
+ dm646x_edma_info[0].rsv_chans = rsv_chans;
+ dm646x_edma_info[0].rsv_slots = rsv_slots;
+
+ return platform_device_register(&dm646x_edma_device);
+}
+
void __init dm646x_init(void)
{
dm646x_board_setup_refclk(&ref_clk);
@@ -923,7 +932,6 @@ static int __init dm646x_init_devices(void)
if (!cpu_is_davinci_dm646x())
return 0;
- platform_device_register(&dm646x_edma_device);
platform_device_register(&dm646x_emac_device);
return 0;
}
@@ -32,6 +32,9 @@ void __init dm646x_init_ide(void);
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
void __init dm646x_board_setup_refclk(struct clk *clk);
+int __init dm646x_init_edma(const s16 (*rsv_chans)[2],
+ const s16 (*rsv_slots)[2]);
+
void dm646x_video_init(void);