@@ -187,6 +187,59 @@ enum DA830_edma_ch {
DA830_DMACH_UART2_TX
};
+/* TNETV107X specific EDMA3 information */
+#define EDMA_TNETV107X_NUM_DMACH 64
+#define EDMA_TNETV107X_NUM_TCC 64
+#define EDMA_TNETV107X_NUM_PARAMENTRY 128
+#define EDMA_TNETV107X_NUM_EVQUE 2
+#define EDMA_TNETV107X_NUM_TC 2
+#define EDMA_TNETV107X_CHMAP_EXIST 0
+#define EDMA_TNETV107X_NUM_REGIONS 4
+#define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u
+#define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu
+
+/* TNETV107X specific EDMA3 Events Information */
+enum tnetv107x_edma_ch {
+ TNETV107X_DMACH_AES_DMAREQIN = 3,
+ TNETV107X_DMACH_AES_DMAREQOUT = 4,
+ TNETV107X_DMACH_DES_DMAREQIN = 5,
+ TNETV107X_DMACH_DES_DMAREQOUT = 6,
+ TNETV107X_DMACH_SHA = 7,
+ TNETV107X_DMACH_IMCOP_IMX = 8,
+ TNETV107X_DMACH_IMCOP_VLCD = 9,
+ TNETV107X_DMACH_IMCOP_SQR_ARM = 10,
+ TNETV107X_DMACH_IMCOP_SQR_DSP = 11,
+ TNETV107X_DMACH_PKA = 13,
+ TNETV107X_DMACH_MDIO = 14,
+ TNETV107X_DMACH_SSP = 15,
+ TNETV107X_DMACH_UART1_RX = 18,
+ TNETV107X_DMACH_UART1_TX = 19,
+ TNETV107X_DMACH_SDIO0_RX = 26,
+ TNETV107X_DMACH_SDIO0_TX = 27,
+ TNETV107X_DMACH_SDIO1_RX = 28,
+ TNETV107X_DMACH_SDIO1_TX = 29,
+ TNETV107X_DMACH_GPIO00 = 32,
+ TNETV107X_DMACH_GPIO01 = 33,
+ TNETV107X_DMACH_GPIO02 = 34,
+ TNETV107X_DMACH_GPIO03 = 35,
+ TNETV107X_DMACH_EXT0 = 44,
+ TNETV107X_DMACH_EXT1 = 45,
+ TNETV107X_DMACH_GPIO12 = 46,
+ TNETV107X_DMACH_GPIO13 = 47,
+ TNETV107X_DMACH_TIMER00 = 48,
+ TNETV107X_DMACH_TIMER01 = 49,
+ TNETV107X_DMACH_TIMER10 = 50,
+ TNETV107X_DMACH_TIMER11 = 51,
+ TNETV107X_DMACH_TDM0_RXDMA = 52,
+ TNETV107X_DMACH_TDM0_RXMCSP = 53,
+ TNETV107X_DMACH_TDM0_TXDMA = 54,
+ TNETV107X_DMACH_TDM0_TXMCSP = 55,
+ TNETV107X_DMACH_TDM1_RXDMA = 56,
+ TNETV107X_DMACH_TDM1_RXMCSP = 57,
+ TNETV107X_DMACH_TDM1_TXDMA = 58,
+ TNETV107X_DMACH_TDM1_TXMCSP = 59,
+};
+
/*ch_status paramater of callback function possible values*/
#define DMA_COMPLETE 1
#define DMA_CC_ERROR 2