diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0316e20..71f90f8 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -50,6 +50,11 @@ config ARCH_DAVINCI_DM365
 	select AINTC
 	select ARCH_DAVINCI_DMx
 
+config ARCH_DAVINCI_TNETV107X
+	select CPU_V6
+	select CP_INTC
+	bool "TNETV107X based system"
+
 comment "DaVinci Board Type"
 
 config MACH_DAVINCI_EVM
@@ -173,6 +178,13 @@ config DA850_UI_RMII
 
 endchoice
 
+config MACH_TNETV107X
+	bool "TI TNETV107X Reference Platform"
+	default ARCH_DAVINCI_TNETV107X
+	depends on ARCH_DAVINCI_TNETV107X
+	help
+	  Say Y here to select the TI TNETV107X Evaluation Module.
+
 config DAVINCI_MUX
 	bool "DAVINCI multiplexing support"
 	depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 6aac880..ca01d56 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
+obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
 
 obj-$(CONFIG_AINTC)			+= irq.o
 obj-$(CONFIG_CP_INTC)			+= cp_intc.o
@@ -30,6 +31,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)	+= board-dm646x-evm.o cdce949.o
 obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
+obj-$(CONFIG_MACH_TNETV107X)		+= board-tnetv107x-evm.o
 
 # Power Management
 obj-$(CONFIG_CPU_FREQ)			+= cpufreq.o
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
new file mode 100644
index 0000000..3704006
--- /dev/null
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -0,0 +1,270 @@
+/*
+ * TI TNETV107X EVM board
+ *
+ * Author: Cyril Chemparathy <cyril@ti.com>
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Derived from: arch/arm/mach-davinci/board-da830-evm.c
+ * Original copyrights follow.
+ *
+ * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/serial_8250.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/mmc.h>
+#include <mach/serial.h>
+#include <mach/mux.h>
+#include <mach/nand.h>
+#include <mach/tnetv107x.h>
+
+#define TNETV107X_EVM_MMC_WP_GPIO	TNETV107X_GPIO(21)
+#define TNETV107X_EVM_MMC_CD_GPIO	TNETV107X_GPIO(24)
+
+static struct plat_serial8250_port tnetv107x_serial_pdata[] = {
+	{
+		.mapbase	= TNETV107X_UART0_BASE,
+		.irq		= IRQ_TNETV107X_UART0,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.mapbase	= TNETV107X_UART1_BASE,
+		.irq		= IRQ_TNETV107X_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.flags	= 0,
+	},
+};
+
+static struct platform_device tnetv107x_serial_device = {
+	.name			= "serial8250",
+	.id			= PLAT8250_DEV_PLATFORM,
+	.dev			= {
+		.platform_data	= tnetv107x_serial_pdata,
+	},
+};
+
+static int tnetv107x_evm_mmc_get_ro(int index)
+{
+	return gpio_get_value(TNETV107X_EVM_MMC_WP_GPIO);
+}
+
+static int tnetv107x_evm_mmc_get_cd(int index)
+{
+	return !gpio_get_value(TNETV107X_EVM_MMC_CD_GPIO);
+}
+
+static struct resource tnetv107x_evm_mmc_resources[] = {
+	{ /* Memory mapped registers */
+		.start	= TNETV107X_SDIO1_BASE,
+		.end	= TNETV107X_SDIO1_BASE + 0x0ff,
+		.flags	= IORESOURCE_MEM
+	},
+	{ /* MMC interrupt */
+		.start	= IRQ_TNETV107X_MMC1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* SDIO interrupt */
+		.start	= IRQ_TNETV107X_SDIO1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* DMA RX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
+		.flags	= IORESOURCE_DMA
+	},
+	{ /* DMA TX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
+		.flags	= IORESOURCE_DMA
+	},
+};
+
+static struct davinci_mmc_config tnetv107x_evm_mmc_config = {
+	.get_cd		= tnetv107x_evm_mmc_get_cd,
+	.get_ro		= tnetv107x_evm_mmc_get_ro,
+	.wires		= 4,
+	.max_freq	= 50000000,
+	.caps		= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+	.version	= MMC_CTLR_VERSION_1,
+};
+
+static u64 tnetv107x_evm_mmc_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device tnetv107x_evm_mmc_device = {
+	.name		= "davinci_mmc",
+	.id		= 1,
+	.dev		= {
+		.dma_mask		= &tnetv107x_evm_mmc_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &tnetv107x_evm_mmc_config,
+	},
+	.num_resources	= ARRAY_SIZE(tnetv107x_evm_mmc_resources),
+	.resource	= tnetv107x_evm_mmc_resources
+};
+
+static const short tnetv107x_sdio1_pins[] = {
+	TNETV107X_SDIO1_CLK_1,		TNETV107X_SDIO1_CMD_1,
+	TNETV107X_SDIO1_DATA0_1,	TNETV107X_SDIO1_DATA1_1,
+	TNETV107X_SDIO1_DATA2_1,	TNETV107X_SDIO1_DATA3_1,
+	-1
+};
+
+const short tnetv107x_uart1_pins[] = {
+	TNETV107X_UART1_RD,		TNETV107X_UART1_TD,
+	-1
+};
+
+static const short tnetv107x_gpio_pins[] = {
+	TNETV107X_GPIO21, TNETV107X_GPIO24, TNETV107X_GPIO23,
+	-1
+};
+
+static struct mtd_partition tnetv107x_evm_nand_partitions[] = {
+	/* bootloader (U-Boot, etc) in first 12 sectors */
+	{
+		.name		= "bootloader",
+		.offset		= 0,
+		.size		= (12*SZ_128K),
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* bootloader params in the next sector */
+	{
+		.name		= "params",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* kernel */
+	{
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_4M,
+		.mask_flags	= 0,
+	},
+	/* file system */
+	{
+		.name		= "filesystem",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= MTDPART_SIZ_FULL,
+		.mask_flags	= 0,
+	}
+};
+
+static struct davinci_nand_pdata tnetv107x_evm_nand_data = {
+	.mask_cle	= 0x4000,
+	.mask_ale	= 0x2000,
+	.parts		= tnetv107x_evm_nand_partitions,
+	.nr_parts	= ARRAY_SIZE(tnetv107x_evm_nand_partitions),
+	.ecc_mode	= NAND_ECC_HW,
+};
+
+static struct resource tnetv107x_evm_nand_resources[] = {
+	{
+		.start		= TNETV107X_ASYNC_EMIF_DATA_CE0_BASE,
+		.end		= TNETV107X_ASYNC_EMIF_DATA_CE0_BASE +
+					SZ_16M - 1,
+		.flags		= IORESOURCE_MEM,
+	},
+	{
+		.start		= TNETV107X_ASYNC_EMIF_CNTRL_BASE,
+		.end		= TNETV107X_ASYNC_EMIF_CNTRL_BASE +
+					SZ_4K - 1,
+		.flags		= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device tnetv107x_evm_nand_device = {
+	.name		= "davinci_nand",
+	.id		= 0,	/* chip select 0 */
+	.dev		= {
+		.platform_data	= &tnetv107x_evm_nand_data,
+	},
+	.num_resources	= ARRAY_SIZE(tnetv107x_evm_nand_resources),
+	.resource	= tnetv107x_evm_nand_resources,
+};
+
+static struct platform_device *tnetv107x_evm_devices[] __initdata = {
+	&tnetv107x_serial_device,
+	&tnetv107x_evm_nand_device,
+	&tnetv107x_evm_mmc_device,
+};
+
+static __init void tnetv107x_evm_board_init(void)
+{
+	int status;
+
+	davinci_cfg_reg_list(tnetv107x_sdio1_pins);
+	davinci_cfg_reg_list(tnetv107x_uart1_pins);
+	davinci_cfg_reg_list(tnetv107x_gpio_pins);
+
+	status = gpio_request(TNETV107X_EVM_MMC_WP_GPIO, "MMC WP\n");
+	if (status < 0) {
+		printk(KERN_ERR "cannot open mmcsd write protect gpio %d\n",
+				TNETV107X_EVM_MMC_WP_GPIO);
+		tnetv107x_evm_mmc_config.get_ro = NULL;
+	} else
+		gpio_direction_input(TNETV107X_EVM_MMC_WP_GPIO);
+
+	status = gpio_request(TNETV107X_EVM_MMC_CD_GPIO, "MMC CD\n");
+	if (status < 0) {
+		printk(KERN_ERR "cannot open mmcsd card detect gpio %d\n",
+				TNETV107X_EVM_MMC_CD_GPIO);
+		tnetv107x_evm_mmc_config.get_cd = NULL;
+	} else
+		gpio_direction_input(TNETV107X_EVM_MMC_CD_GPIO);
+
+	tnetv107x_edma_init();
+
+	tnetv107x_serial_init(tnetv107x_serial_pdata);
+
+	platform_add_devices(tnetv107x_evm_devices,
+				ARRAY_SIZE(tnetv107x_evm_devices));
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init tnetv107x_evm_console_init(void)
+{
+	return add_preferred_console("ttyS", 1, "115200");
+}
+console_initcall(tnetv107x_evm_console_init);
+#endif
+
+static void __init map_io(void)
+{
+	tnetv107x_init();
+}
+
+MACHINE_START(TNETV107X, "TNETV107X EVM")
+	.phys_io	= TNETV107X_IO_BASE,
+	.io_pg_offst	= (TNETV107X_IO_VIRT >> 18) & 0xfffc,
+	.boot_params	= (TNETV107X_DDR_BASE + 0x100),
+	.map_io		= map_io,
+	.init_irq	= tnetv107x_irq_init,
+	.timer		= &davinci_timer,
+	.init_machine	= tnetv107x_evm_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
new file mode 100644
index 0000000..0d65ba6
--- /dev/null
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -0,0 +1,275 @@
+/*
+ * TI TNETV107X platform devices
+ *
+ * Author: Cyril Chemparathy <cyril@ti.com>
+ *
+ * 2009 (c) Texas Instruments, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/serial.h>
+#include <mach/tnetv107x.h>
+
+#include "clock.h"
+
+struct tnetv107x_gpio_regs {
+	u32	idver;
+	u32	data_in[3];
+	u32	data_out[3];
+	u32	direction[3];
+	u32	enable[3];
+};
+
+struct tnetv107x_gpio_controller {
+	struct tnetv107x_gpio_regs __iomem *regs;
+	struct gpio_chip	chip;
+};
+
+#define gpio_reg_index(gpio)	((gpio) >> 5)
+#define gpio_reg_bit(gpio)	BIT((gpio) & 0x1f)
+
+#define gpio_reg_rmw(reg, mask, val)	\
+	__raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
+
+#define gpio_reg_set_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
+
+#define gpio_reg_clear_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
+
+#define gpio_reg_get_bit(reg, gpio)	\
+	(__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
+
+#define chip_to_gpio(chip)		\
+	container_of(chip, struct tnetv107x_gpio_controller, chip)
+
+static struct tnetv107x_gpio_controller tnetv107x_gpio_controller;
+
+static struct resource wdt_resources[] = {
+	{
+		.start	= TNETV107X_TIMER1_BASE,
+		.end	= TNETV107X_TIMER1_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device davinci_wdt_device = {
+	.name		= "watchdog",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(wdt_resources),
+	.resource	= wdt_resources,
+};
+
+static const s8 edma_tc_mapping[][2] = {
+	/* event queue no	TC no	*/
+	{	 0,		 0	},
+	{	 1,		 1	},
+	{	-1,		-1	}
+};
+
+static const s8 edma_priority_mapping[][2] = {
+	/* event queue no	Prio	*/
+	{	 0,		 3	},
+	{	 1,		 7	},
+	{	-1,		-1	}
+};
+
+static struct edma_soc_info edma_info[] = {
+	{
+		.n_channel		= 32,
+		.n_region		= 4,
+		.n_slot			= 128,
+		.n_tc			= 2,
+		.n_cc			= 1,
+		.queue_tc_mapping	= edma_tc_mapping,
+		.queue_priority_mapping	= edma_priority_mapping,
+	},
+};
+
+static struct resource edma_resources[] = {
+	{
+		.name	= "edma_cc0",
+		.start	= TNETV107X_TPCC_BASE,
+		.end	= TNETV107X_TPCC_BASE + SZ_32K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc0",
+		.start	= TNETV107X_TPTC0_BASE,
+		.end	= TNETV107X_TPTC0_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc1",
+		.start	= TNETV107X_TPTC1_BASE,
+		.end	= TNETV107X_TPTC1_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma0",
+		.start	= IRQ_TNETV107X_TPCC,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "edma0_err",
+		.start	= IRQ_TNETV107X_TPCC_ERR,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device edma_device = {
+	.name		= "edma",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(edma_resources),
+	.resource	= edma_resources,
+	.dev.platform_data = edma_info,
+};
+
+static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned gpio)
+{
+	struct tnetv107x_gpio_controller *ctlr = chip_to_gpio(chip);
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	gpio_reg_set_bit(&ctlr->regs->enable, gpio);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned gpio)
+{
+	struct tnetv107x_gpio_controller *ctlr = chip_to_gpio(chip);
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	gpio_reg_clear_bit(&ctlr->regs->enable, gpio);
+
+	local_irq_restore(flags);
+}
+
+static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
+{
+	struct tnetv107x_gpio_controller *ctlr = chip_to_gpio(chip);
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	gpio_reg_set_bit(&ctlr->regs->direction, gpio);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
+		unsigned gpio, int value)
+{
+	struct tnetv107x_gpio_controller *ctlr = chip_to_gpio(chip);
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	if (value)
+		gpio_reg_set_bit(&ctlr->regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&ctlr->regs->data_out, gpio);
+
+	gpio_reg_clear_bit(&ctlr->regs->direction, gpio);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned gpio)
+{
+	struct tnetv107x_gpio_controller *ctlr = chip_to_gpio(chip);
+	int ret;
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	ret = gpio_reg_get_bit(&ctlr->regs->data_in, gpio);
+
+	local_irq_restore(flags);
+
+	return ret ? 1 : 0;
+}
+
+static void tnetv107x_gpio_set(struct gpio_chip *chip,
+		unsigned gpio, int value)
+{
+	struct tnetv107x_gpio_controller *ctlr = chip_to_gpio(chip);
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	if (value)
+		gpio_reg_set_bit(&ctlr->regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&ctlr->regs->data_out, gpio);
+
+	local_irq_restore(flags);
+}
+
+static int __init tnetv107x_gpio_setup(void)
+{
+	struct tnetv107x_gpio_controller *ctlr = &tnetv107x_gpio_controller;
+
+	ctlr->regs = ioremap(TNETV107X_GPIO_BASE, PAGE_SIZE);
+
+	ctlr->chip.label		= "TNETV107X";
+	ctlr->chip.request		= tnetv107x_gpio_request;
+	ctlr->chip.free			= tnetv107x_gpio_free;
+	ctlr->chip.direction_input	= tnetv107x_gpio_dir_in;
+	ctlr->chip.get			= tnetv107x_gpio_get;
+	ctlr->chip.direction_output	= tnetv107x_gpio_dir_out;
+	ctlr->chip.set			= tnetv107x_gpio_set;
+	ctlr->chip.base			= TNETV107X_GPIO(0);
+	ctlr->chip.ngpio		= TNETV107X_N_GPIOS;
+	ctlr->chip.can_sleep		= 0;
+
+	gpiochip_add(&ctlr->chip);
+
+	return 0;
+}
+pure_initcall(tnetv107x_gpio_setup);
+
+void __init tnetv107x_edma_init(void)
+{
+	platform_device_register(&edma_device);
+}
+
+void __init tnetv107x_serial_init(struct plat_serial8250_port* ports)
+{
+	int i;
+	char name[16];
+	struct clk *uart_clk;
+
+	for (i = 0; ports[i].flags; i++) {
+		sprintf(name, "uart%d", i);
+		uart_clk = clk_get(NULL, name);
+		if (IS_ERR(uart_clk))
+			printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
+					__func__, __LINE__, i);
+		else {
+			clk_enable(uart_clk);
+			ports[i].uartclk = clk_get_rate(uart_clk);
+		}
+	}
+}
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index b8b47a4..35860af 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -32,6 +32,15 @@
 #define UART_VIRT	IO_ADDRESS(UART_PHYS)
 #endif
 
+#if defined(CONFIG_ARCH_DAVINCI_TNETV107X)
+#include <mach/tnetv107x.h>
+#ifdef UART_PHYS
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
+#endif
+#define UART_PHYS	TNETV107X_UART1_BASE
+#define UART_VIRT	TNETV107X_UART1_VIRT
+#endif
+
 #define UART_SHIFT	2
 
 		.macro addruart, rx, tmp
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 5b6c597..d882a3c 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
 #define __ASM_ARCH_DAVINCI_TNETV107X_H
 
+#include <asm/sizes.h>
+
 /* Base addresses for on-chip devices */
 #define TNETV107X_TPCC_BASE			0x01c00000
 #define TNETV107X_TPTC0_BASE			0x01c10000
@@ -61,13 +63,58 @@
 #define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
 #define TNETV107X_DDR_BASE			0x80000000
 
+/* Fixed mapping for early init starts here */
+#define TNETV107X_IO_BASE	0x08000000
+#define TNETV107X_IO_VIRT	(IO_VIRT + SZ_2M)
+#define TNETV107X_IO_OFFSET	(TNETV107X_IO_VIRT - TNETV107X_IO_BASE)
+#define TNETV107X_UART1_VIRT	(TNETV107X_UART1_BASE + TNETV107X_IO_OFFSET)
+
 /* Boot Configuration Parameters */
 #define TNETV107X_KICK0		(TNETV107X_CHIP_CFG_BASE + 0x38)
 #define TNETV107X_KICK1		(TNETV107X_CHIP_CFG_BASE + 0x3c)
 #define TNETV107X_KICK0_MAGIC	0x83e70b13
 #define TNETV107X_KICK1_MAGIC	0x95a4f1e0
 
+#define PINMUX0		(0 << 2)
+#define PINMUX1		(1 << 2)
+#define PINMUX2		(2 << 2)
+#define PINMUX3		(3 << 2)
+#define PINMUX4		(4 << 2)
+#define PINMUX5		(5 << 2)
+#define PINMUX6		(6 << 2)
+#define PINMUX7		(7 << 2)
+#define PINMUX8		(8 << 2)
+#define PINMUX9		(9 << 2)
+#define PINMUX10	(10 << 2)
+#define PINMUX11	(11 << 2)
+#define PINMUX12	(12 << 2)
+#define PINMUX13	(13 << 2)
+#define PINMUX14	(14 << 2)
+#define PINMUX15	(15 << 2)
+#define PINMUX16	(16 << 2)
+#define PINMUX17	(17 << 2)
+#define PINMUX18	(18 << 2)
+#define PINMUX19	(19 << 2)
+#define PINMUX20	(20 << 2)
+#define PINMUX21	(21 << 2)
+#define PINMUX22	(22 << 2)
+#define PINMUX23	(23 << 2)
+#define PINMUX24	(24 << 2)
+#define PINMUX25	(25 << 2)
+#define PINMUX26	(26 << 2)
+
 #define TNETV107X_N_GPIOS	65
+#define TNETV107X_GPIO(x)	((x) + DAVINCI_N_GPIO)
+
+#ifndef __ASSEMBLY__
+
+#include <linux/serial_8250.h>
+
+extern void __init tnetv107x_init(void);
+extern void __init tnetv107x_edma_init(void);
+extern void __init tnetv107x_irq_init(void);
+extern void __init tnetv107x_serial_init(struct plat_serial8250_port* ports);
+#endif
 
 #endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
 
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
new file mode 100644
index 0000000..d79092a
--- /dev/null
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -0,0 +1,1215 @@
+/*
+ * TI TNETV107X chip specific setup
+ *
+ * Author: Cyril Chemparathy <cyril@ti.com>
+ *
+ * 2009 (c) Texas Instruments, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * TNETV107X clock control implementation doesn't (at this point) reuse
+ * much of Davinci's generic implementation. This is because of the
+ * SSPLL nastiness that is present on this part.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/time.h>
+#include <mach/cputype.h>
+#include <mach/psc.h>
+#include <mach/cp_intc.h>
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/tnetv107x.h>
+
+#include "clock.h"
+#include "mux.h"
+
+/* Reference clock frequencies */
+#define OSC_FREQ_ONCHIP		(24000 * 1000)
+#define OSC_FREQ_OFFCHIP_SYS	(25000 * 1000)
+#define OSC_FREQ_OFFCHIP_ETH	(25000 * 1000)
+#define OSC_FREQ_OFFCHIP_TDM	(19200 * 1000)
+
+/* PLL Types */
+enum pll_type {
+	SYS_PLL,
+	TDM_PLL,
+	ETH_PLL,
+	N_PLLS
+};
+
+/* Clock Control Registers */
+struct clk_ctrl_regs {
+	u32	pll_bypass;
+	u32	_reserved0;
+	u32	gem_lrst;
+	u32	_reserved1;
+	u32	pll_unlock_stat;
+	u32	sys_unlock;
+	u32	eth_unlock;
+	u32	tdm_unlock;
+};
+
+/* SSPLL Registers */
+struct sspll_regs {
+	u32	modes;
+	u32	post_div;
+	u32	pre_div;
+	u32	mult_factor;
+	u32	divider_range;
+	u32	bw_divider;
+	u32	spr_amount;
+	u32	spr_rate_div;
+	u32	diag;
+};
+
+static struct clk_ctrl_regs __iomem *clk_ctrl_regs;
+
+static struct sspll_regs __iomem *sspll_regs[N_PLLS];
+static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 };
+
+/* PLL Control Registers (same as in Davinci) */
+static void __iomem *pllctl_regs[N_PLLS];
+static int pllctl_regs_base[N_PLLS] = { 0x600, 0x200, 0x400 };
+
+/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */
+static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) };
+
+/* different PLLs have different limits on the divider max */
+static u32 div_mask[] = {0x01ff, 0x00ff, 0x00ff};
+
+/* offchip (external) reference clock frequencies */
+static u32 pll_ext_freq[] = {
+	OSC_FREQ_OFFCHIP_SYS,
+	OSC_FREQ_OFFCHIP_TDM,
+	OSC_FREQ_OFFCHIP_ETH
+};
+
+/* PSC control registers */
+static void __iomem *psc_regs[1];
+
+/* Host map for interrupt controller */
+static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
+
+static unsigned long clk_sspll_recalc(struct clk *clk);
+static unsigned long clk_div_recalc(struct clk *clk);
+static unsigned long clk_null_recalc(struct clk *clk);
+
+static struct pll_data pll_sys_data = { .num = SYS_PLL };
+static struct pll_data pll_eth_data = { .num = ETH_PLL };
+static struct pll_data pll_tdm_data = { .num = TDM_PLL };
+
+/* Top level of the clock tree - the PLLs */
+static struct clk pll_sys_clk = {
+	.name		= "pll_sys",
+	.pll_data	= &pll_sys_data,
+	.flags		= CLK_PLL,
+	.recalc		= clk_sspll_recalc,
+};
+
+static struct clk pll_eth_clk = {
+	.name		= "pll_eth",
+	.pll_data	= &pll_eth_data,
+	.flags		= CLK_PLL,
+	.recalc		= clk_sspll_recalc,
+};
+
+static struct clk pll_tdm_clk = {
+	.name		= "pll_tdm",
+	.pll_data	= &pll_tdm_data,
+	.flags		= CLK_PLL,
+	.recalc		= clk_sspll_recalc,
+};
+
+
+/* System PLL Dividers */
+static struct clk sys_arm1176_clk = {
+	.name		= "sys_arm1176_clk",
+	.parent		= &pll_sys_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV1,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk sys_dsp_clk = {
+	.name		= "sys_dsp_clk",
+	.parent		= &pll_sys_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV2,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk sys_ddr_clk = {
+	.name		= "sys_ddr_clk",
+	.parent		= &pll_sys_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV3,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk sys_full_clk = {
+	.name		= "sys_full_clk",
+	.parent		= &pll_sys_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV4,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk sys_lcd_clk = {
+	.name		= "sys_lcd_clk",
+	.parent		= &pll_sys_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV5,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk sys_vlynq_ref_clk = {
+	.name		= "sys_vlynq_ref_clk",
+	.parent		= &pll_sys_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV6,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk sys_tsc_clk = {
+	.name		= "sys_tsc_clk",
+	.parent		= &pll_sys_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV7,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk sys_half_clk = {
+	.name		= "sys_half_clk",
+	.parent		= &pll_sys_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV8,
+	.recalc		= clk_div_recalc,
+};
+
+
+/* Ethernet PLL Dividers */
+static struct clk eth_clk_5 = {
+	.name		= "eth_clk_5",
+	.parent		= &pll_eth_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV1,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk eth_clk_50 = {
+	.name		= "eth_clk_50",
+	.parent		= &pll_eth_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV2,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk eth_clk_125 = {
+	.name		= "eth_clk_125",
+	.parent		= &pll_eth_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV3,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk eth_clk_250 = {
+	.name		= "eth_clk_250",
+	.parent		= &pll_eth_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV4,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk eth_clk_25 = {
+	.name		= "eth_clk_25",
+	.parent		= &pll_eth_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV5,
+	.recalc		= clk_div_recalc,
+};
+
+
+/* TDM PLL Dividers */
+static struct clk tdm_0_clk = {
+	.name		= "tdm_0_clk",
+	.parent		= &pll_tdm_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV1,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk tdm_extra_clk = {
+	.name		= "tdm_extra_clk",
+	.parent		= &pll_tdm_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV2,
+	.recalc		= clk_div_recalc,
+};
+
+static struct clk tdm_1_clk = {
+	.name		= "tdm_1_clk",
+	.parent		= &pll_tdm_clk,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV3,
+	.recalc		= clk_div_recalc,
+};
+
+
+/* LPSC Gated Clocks */
+static struct clk clk_arm = {
+	.name		= "clk_arm",
+	.parent		= &sys_arm1176_clk,
+	.lpsc		= TNETV107X_LPSC_ARM,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_gem = {
+	.name		= "clk_gem",
+	.parent		= &sys_dsp_clk,
+	.lpsc		= TNETV107X_LPSC_GEM,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_ddr2_phy = {
+	.name		= "clk_ddr2_phy",
+	.parent		= &sys_ddr_clk,
+	.lpsc		= TNETV107X_LPSC_DDR2_PHY,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_tpcc = {
+	.name		= "clk_tpcc",
+	.parent		= &sys_full_clk,
+	.lpsc		= TNETV107X_LPSC_TPCC,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_tptc0 = {
+	.name		= "clk_tptc0",
+	.parent		= &sys_full_clk,
+	.lpsc		= TNETV107X_LPSC_TPTC0,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_tptc1 = {
+	.name		= "clk_tptc1",
+	.parent		= &sys_full_clk,
+	.lpsc		= TNETV107X_LPSC_TPTC1,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_ram = {
+	.name		= "clk_ram",
+	.parent		= &sys_full_clk,
+	.lpsc		= TNETV107X_LPSC_RAM,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_mbx_lite = {
+	.name		= "clk_mbx_lite",
+	.parent		= &sys_arm1176_clk,
+	.lpsc		= TNETV107X_LPSC_MBX_LITE,
+};
+
+static struct clk clk_lcd = {
+	.name		= "clk_lcd",
+	.parent		= &sys_lcd_clk,
+	.lpsc		= TNETV107X_LPSC_LCD,
+	.flags		= PSC_SWRSTDISABLE,
+};
+
+static struct clk clk_ethss = {
+	.name		= "clk_ethss",
+	.parent		= &eth_clk_125,
+	.lpsc		= TNETV107X_LPSC_ETHSS,
+};
+
+static struct clk clk_aemif = {
+	.name		= "clk_aemif",
+	.parent		= &sys_full_clk,
+	.lpsc		= TNETV107X_LPSC_AEMIF,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_chip_cfg = {
+	.name		= "clk_chip_cfg",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_CHIP_CFG,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_tsc = {
+	.name		= "clk_tsc",
+	.parent		= &sys_tsc_clk,
+	.lpsc		= TNETV107X_LPSC_TSC,
+};
+
+static struct clk clk_rom = {
+	.name		= "clk_rom",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_ROM,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_uart2 = {
+	.name		= "uart2",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_UART2,
+};
+
+static struct clk clk_pktsec = {
+	.name		= "clk_pktsec",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_PKTSEC,
+};
+
+static struct clk clk_rng = {
+	.name		= "clk_rng",
+	.parent		= &clk_pktsec,
+	.recalc		= clk_null_recalc,
+};
+
+static struct clk clk_pka = {
+	.name		= "clk_pka",
+	.parent		= &clk_pktsec,
+	.recalc		= clk_null_recalc,
+};
+
+static struct clk clk_secctl = {
+	.name		= "clk_secctl",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_SECCTL,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_keymgr = {
+	.name		= "clk_keymgr",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_KEYMGR,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_keypad = {
+	.name		= "clk_keypad",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_KEYPAD,
+};
+
+static struct clk clk_gpio = {
+	.name		= "clk_gpio",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_GPIO,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_mdio = {
+	.name		= "clk_mdio",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_MDIO,
+};
+
+static struct clk clk_sdio0 = {
+	.name		= "clk_sdio0",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_SDIO0,
+};
+
+static struct clk clk_uart0 = {
+	.name		= "uart0",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_UART0,
+};
+
+static struct clk clk_uart1 = {
+	.name		= "uart1",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_UART1,
+};
+
+static struct clk clk_timer0 = {
+	.name		= "timer0",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_TIMER0,
+};
+
+static struct clk clk_timer1 = {
+	.name		= "timer1",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_TIMER1,
+};
+
+static struct clk clk_wdt_arm = {
+	.name		= "clk_wdt_arm",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_WDT_ARM,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_wdt_dsp = {
+	.name		= "clk_wdt_dsp",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_WDT_DSP,
+};
+
+static struct clk clk_ssp = {
+	.name		= "clk_ssp",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_SSP,
+};
+
+static struct clk clk_tdm0 = {
+	.name		= "clk_tdm0",
+	.parent		= &tdm_0_clk,
+	.lpsc		= TNETV107X_LPSC_TDM0,
+};
+
+static struct clk clk_vlynq = {
+	.name		= "clk_vlynq",
+	.parent		= &sys_vlynq_ref_clk,
+	.lpsc		= TNETV107X_LPSC_VLYNQ,
+};
+
+static struct clk clk_mcdma = {
+	.name		= "clk_mcdma",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_MCDMA,
+};
+
+static struct clk clk_usb0 = {
+	.name		= "clk_usb0",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_USB0,
+};
+
+static struct clk clk_tdm1 = {
+	.name		= "clk_tdm1",
+	.parent		= &tdm_1_clk,
+	.lpsc		= TNETV107X_LPSC_TDM1,
+};
+
+static struct clk clk_debugss = {
+	.name		= "clk_debugss",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_DEBUGSS,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_ethss_rgmii = {
+	.name		= "clk_ethss_rgmii",
+	.parent		= &eth_clk_250,
+	.lpsc		= TNETV107X_LPSC_ETHSS_RGMII,
+};
+
+static struct clk clk_system = {
+	.name		= "clk_system",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_SYSTEM,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_imcop = {
+	.name		= "clk_imcop",
+	.parent		= &sys_dsp_clk,
+	.lpsc		= TNETV107X_LPSC_IMCOP,
+};
+
+static struct clk clk_spare = {
+	.name		= "clk_spare",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_SPARE,
+};
+
+static struct clk clk_sdio1 = {
+	.name		= "clk_sdio1",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_SDIO1,
+};
+
+static struct clk clk_usb1 = {
+	.name		= "clk_usb1",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_USB1,
+};
+
+static struct clk clk_usbss = {
+	.name		= "clk_usbss",
+	.parent		= &sys_half_clk,
+	.lpsc		= TNETV107X_LPSC_USBSS,
+};
+
+static struct clk clk_ddr2_vrst = {
+	.name		= "clk_ddr2_vrst",
+	.parent		= &sys_ddr_clk,
+	.lpsc		= TNETV107X_LPSC_DDR2_EMIF1_VRST,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk clk_ddr2_vctl_rst = {
+	.name		= "clk_ddr2_vctl_rst",
+	.parent		= &sys_ddr_clk,
+	.lpsc		= TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST,
+	.flags		= ALWAYS_ENABLED,
+};
+
+static struct clk_lookup tnetv107x_clks[] = {
+	CLK(NULL,		"pll_sys_clk",		&pll_sys_clk),
+	CLK(NULL,		"pll_eth_clk",		&pll_eth_clk),
+	CLK(NULL,		"pll_tdm_clk",		&pll_tdm_clk),
+	CLK(NULL,		"sys_arm1176_clk",	&sys_arm1176_clk),
+	CLK(NULL,		"sys_dsp_clk",		&sys_dsp_clk),
+	CLK(NULL,		"sys_ddr_clk",		&sys_ddr_clk),
+	CLK(NULL,		"sys_full_clk",		&sys_full_clk),
+	CLK(NULL,		"sys_lcd_clk",		&sys_lcd_clk),
+	CLK(NULL,		"sys_vlynq_ref_clk",	&sys_vlynq_ref_clk),
+	CLK(NULL,		"sys_tsc_clk",		&sys_tsc_clk),
+	CLK(NULL,		"sys_half_clk",		&sys_half_clk),
+	CLK(NULL,		"eth_clk_5",		&eth_clk_5),
+	CLK(NULL,		"eth_clk_50",		&eth_clk_50),
+	CLK(NULL,		"eth_clk_125",		&eth_clk_125),
+	CLK(NULL,		"eth_clk_250",		&eth_clk_250),
+	CLK(NULL,		"eth_clk_25",		&eth_clk_25),
+	CLK(NULL,		"tdm_0_clk",		&tdm_0_clk),
+	CLK(NULL,		"tdm_extra_clk",	&tdm_extra_clk),
+	CLK(NULL,		"tdm_1_clk",		&tdm_1_clk),
+	CLK(NULL,		"clk_arm",		&clk_arm),
+	CLK(NULL,		"clk_gem",		&clk_gem),
+	CLK(NULL,		"clk_ddr2_phy",		&clk_ddr2_phy),
+	CLK(NULL,		"clk_tpcc",		&clk_tpcc),
+	CLK(NULL,		"clk_tptc0",		&clk_tptc0),
+	CLK(NULL,		"clk_tptc1",		&clk_tptc1),
+	CLK(NULL,		"clk_ram",		&clk_ram),
+	CLK(NULL,		"clk_mbx_lite",		&clk_mbx_lite),
+	CLK("tnetv107x-fb.0",	NULL,			&clk_lcd),
+	CLK(NULL,		"clk_ethss",		&clk_ethss),
+	CLK(NULL,		"aemif",		&clk_aemif),
+	CLK(NULL,		"clk_chip_cfg",		&clk_chip_cfg),
+	CLK("tnetv107x-ts.0",	NULL,			&clk_tsc),
+	CLK(NULL,		"clk_rom",		&clk_rom),
+	CLK(NULL,		"uart2",		&clk_uart2),
+	CLK(NULL,		"clk_pktsec",		&clk_pktsec),
+	CLK("tnetv107x-rng.0",	NULL,			&clk_rng),
+	CLK("tnetv107x-pka.0",	NULL,			&clk_pka),
+	CLK(NULL,		"clk_secctl",		&clk_secctl),
+	CLK(NULL,		"clk_keymgr",		&clk_keymgr),
+	CLK("tnetv107x-keypad.0", NULL,			&clk_keypad),
+	CLK(NULL,		"clk_gpio",		&clk_gpio),
+	CLK(NULL,		"clk_mdio",		&clk_mdio),
+	CLK("davinci_mmc.0",	NULL,			&clk_sdio0),
+	CLK(NULL,		"uart0",		&clk_uart0),
+	CLK(NULL,		"uart1",		&clk_uart1),
+	CLK(NULL,		"timer0",		&clk_timer0),
+	CLK(NULL,		"timer1",		&clk_timer1),
+	CLK(NULL,		"clk_wdt_arm",		&clk_wdt_arm),
+	CLK(NULL,		"clk_wdt_dsp",		&clk_wdt_dsp),
+	CLK("ti-ssp.0",		NULL,			&clk_ssp),
+	CLK(NULL,		"clk_tdm0",		&clk_tdm0),
+	CLK(NULL,		"clk_vlynq",		&clk_vlynq),
+	CLK(NULL,		"clk_mcdma",		&clk_mcdma),
+	CLK(NULL,		"clk_usb0",		&clk_usb0),
+	CLK(NULL,		"clk_tdm1",		&clk_tdm1),
+	CLK(NULL,		"clk_debugss",		&clk_debugss),
+	CLK(NULL,		"clk_ethss_rgmii",	&clk_ethss_rgmii),
+	CLK(NULL,		"clk_system",		&clk_system),
+	CLK(NULL,		"clk_imcop",		&clk_imcop),
+	CLK(NULL,		"clk_spare",		&clk_spare),
+	CLK("davinci_mmc.1",	NULL,			&clk_sdio1),
+	CLK(NULL,		"clk_usb1",		&clk_usb1),
+	CLK(NULL,		"clk_usbss",		&clk_usbss),
+	CLK(NULL,		"clk_ddr2_vrst",	&clk_ddr2_vrst),
+	CLK(NULL,		"clk_ddr2_vctl_rst",	&clk_ddr2_vctl_rst),
+	CLK(NULL,		NULL,			NULL),
+};
+
+static const struct mux_config tnetv107x_pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+	MUX_CFG(TNETV107X, ASR_A00,		0, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO32,		0, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A01,		0, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO33,		0, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A02,		0, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO34,		0, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A03,		0, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO35,		0, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A04,		0, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO36,		0, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A05,		0, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO37,		0, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A06,		1, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO38,		1, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A07,		1, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO39,		1, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A08,		1, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO40,		1, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A09,		1, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO41,		1, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A10,		1, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO42,		1, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A11,		1, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_0,		1, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A12,		2, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_1,		2, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A13,		2, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO43,		2, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A14,		2, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO44,		2, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A15,		2, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO45,		2, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A16,		2, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO46,		2, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A17,		2, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO47,		2, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_A18,		3, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO48,		3, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA3_0,	3, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A19,		3, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO49,		3, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA2_0,	3, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A20,		3, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO50,		3, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA1_0,	3, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A21,		3, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO51,		3, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA0_0,	3, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A22,		3, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO52,		3, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_CMD_0,		3, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_A23,		3, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO53,		3, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO1_CLK_0,		3, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_BA_1,		4, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO54,		4, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SYS_PLL_CLK,		4, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_CS0,		4, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_CS1,		4, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_CS2,		4, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM_PLL_CLK,		4, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_CS3,		4, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ETH_PHY_CLK,		4, 20, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, ASR_D00,		4, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO55,		4, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D01,		5, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO56,		5, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D02,		5, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO57,		5, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D03,		5, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO58,		5, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D04,		5, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO59_0,		5, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D05,		5, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO60_0,		5, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D06,		5, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO61_0,		5, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D07,		6, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO62_0,		6, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D08,		6, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO63_0,		6, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D09,		6, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO64_0,		6, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D10,		6, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA3_1,	6, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D11,		6, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA2_1,	6, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D12,		6, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA1_1,	6, 25, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D13,		7, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_DATA0_1,	7, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D14,		7, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_CMD_1,		7, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_D15,		7, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SDIO1_CLK_1,		7, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_OE,		7, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_2,		7, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_RNW,		7, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO29_0,		7, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WAIT,		7, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO30_0,		7, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WE,		8, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, BOOT_STRP_3,		8, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, ASR_WE_DQM0,		8, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO31,		8, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD17_0,		8, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, ASR_WE_DQM1,		8, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_BA0_0,		8, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, VLYNQ_CLK,		9, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO14,		9, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD19_0,		9, 0, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_RXD0,		9, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO15,		9, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD20_0,		9, 5, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_RXD1,		9, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO16,		9, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD21_0,		9, 10, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_TXD0,		9, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO17,		9, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD22_0,		9, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, VLYNQ_TXD1,		9, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO18,		9, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD23_0,		9, 20, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, SDIO0_CLK,		10, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO19,		10, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_CMD,		10, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO20,		10, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA0,		10, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO21,		10, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA1,		10, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO22,		10, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA2,		10, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO23,		10, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SDIO0_DATA3,		10, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO24,		10, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, EMU0,		11, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, EMU1,		11, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, RTCK,		12, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TRST_N,		12, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TCK,			12, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDI,			12, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDO,			12, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TMS,			12, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_CLK,		13, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_RX,		13, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_TX,		13, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM1_FS,		13, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R0,		14, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R1,		14, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R2,		14, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R3,		14, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R4,		14, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R5,		14, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_R6,		15, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO12,		15, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, KEYPAD_R7,		15, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO10,		15, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, KEYPAD_C0,		15, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C1,		15, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C2,		15, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C3,		15, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C4,		16, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C5,		16, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, KEYPAD_C6,		16, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO13,		16, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TEST_CLK_IN,		16, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, KEYPAD_C7,		16, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO11,		16, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, SSP0_0,		17, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_DCLK,		17, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD20_1,		17, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_1,		17, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_CS_N,		17, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD21_1,		17, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_2,		17, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_D,		17, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD22_1,		17, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP0_3,		17, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, SCC_RESETN,		17, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, LCD_PD23_1,		17, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_0,		18, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO25,		18, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_CTS,		18, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_1,		18, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO26,		18, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_RD,		18, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_2,		18, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO27,		18, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_RTS,		18, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, SSP1_3,		18, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO28,		18, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, UART2_TD,		18, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, UART0_CTS,		19, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_RD,		19, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_RTS,		19, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART0_TD,		19, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART1_RD,		19, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, UART1_TD,		19, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_AC_NCS,		20, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_HSYNC_RNW,	20, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_VSYNC_A0,	20, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_MCLK,		20, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD16_0,		20, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PCLK_E,		20, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD00,		20, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD01,		21, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD02,		21, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD03,		21, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD04,		21, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD05,		21, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD06,		21, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD07,		22, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD08,		22, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO59_1,		22, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD09,		22, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO60_1,		22, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD10,		22, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, ASR_BA0_1,		22, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO61_1,		22, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD11,		22, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO62_1,		22, 20, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD12,		22, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO63_1,		22, 25, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD13,		23, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO64_1,		23, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD14,		23, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO29_1,		23, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, LCD_PD15,		23, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO30_1,		23, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, EINT0,		24, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO08,		24, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, EINT1,		24, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, GPIO09,		24, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO00,		24, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD20_2,		24, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TDM_CLK_IN_2,	24, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO01,		24, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD21_2,		24, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, 24M_CLK_OUT_1,	24, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO02,		24, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD22_2,		24, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO03,		24, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD23_2,		24, 25, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, GPIO04,		25, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD16_1,		25, 0, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, USB0_RXERR,		25, 0, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO05,		25, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD17_1,		25, 5, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, TDM_CLK_IN_1,	25, 5, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO06,		25, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD18,		25, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, 24M_CLK_OUT_2,	25, 10, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, GPIO07,		25, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, LCD_PD19_1,		25, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, USB1_RXERR,		25, 15, 0x1f, 0x0c, false)
+	MUX_CFG(TNETV107X, ETH_PLL_CLK,		25, 15, 0x1f, 0x1c, false)
+	MUX_CFG(TNETV107X, MDIO,		26, 0, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, MDC,			26, 5, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, AIC_MUTE_STAT_N,	26, 10, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_CLK,		26, 10, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HNS_EN_N,	26, 15, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_FS,		26, 15, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N,	26, 20, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_TX,		26, 20, 0x1f, 0x04, false)
+	MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N,	26, 25, 0x1f, 0x00, false)
+	MUX_CFG(TNETV107X, TDM0_RX,		26, 25, 0x1f, 0x04, false)
+#endif
+};
+
+/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
+static u8 tnetv107x_irq_prios[TNETV107X_N_CP_INTC_IRQ] = {
+	[IRQ_TNETV107X_TDM1_TXDMA]		= 7,
+	[IRQ_TNETV107X_EXT_INT_0]		= 7,
+	[IRQ_TNETV107X_EXT_INT_1]		= 7,
+	[IRQ_TNETV107X_GPIO_INT12]		= 7,
+	[IRQ_TNETV107X_GPIO_INT13]		= 7,
+	[IRQ_TNETV107X_TIMER_0_TINT12]		= 7,
+	[IRQ_TNETV107X_TIMER_1_TINT12]		= 7,
+	[IRQ_TNETV107X_UART0]			= 7,
+	[IRQ_TNETV107X_TDM1_RXDMA]		= 7,
+	[IRQ_TNETV107X_MCDMA_INT0]		= 7,
+	[IRQ_TNETV107X_MCDMA_INT1]		= 7,
+	[IRQ_TNETV107X_TPCC]			= 7,
+	[IRQ_TNETV107X_TPCC_INT0]		= 7,
+	[IRQ_TNETV107X_TPCC_INT1]		= 7,
+	[IRQ_TNETV107X_TPCC_INT2]		= 7,
+	[IRQ_TNETV107X_TPCC_INT3]		= 7,
+	[IRQ_TNETV107X_TPTC0]			= 7,
+	[IRQ_TNETV107X_TPTC1]			= 7,
+	[IRQ_TNETV107X_TIMER_0_TINT34]		= 7,
+	[IRQ_TNETV107X_ETHSS]			= 7,
+	[IRQ_TNETV107X_TIMER_1_TINT34]		= 7,
+	[IRQ_TNETV107X_DSP2ARM_INT0]		= 7,
+	[IRQ_TNETV107X_DSP2ARM_INT1]		= 7,
+	[IRQ_TNETV107X_ARM_NPMUIRQ]		= 7,
+	[IRQ_TNETV107X_USB1]			= 7,
+	[IRQ_TNETV107X_VLYNQ]			= 7,
+	[IRQ_TNETV107X_UART0_DMATX]		= 7,
+	[IRQ_TNETV107X_UART0_DMARX]		= 7,
+	[IRQ_TNETV107X_TDM1_TXMCSP]		= 7,
+	[IRQ_TNETV107X_SSP]			= 7,
+	[IRQ_TNETV107X_MCDMA_INT2]		= 7,
+	[IRQ_TNETV107X_MCDMA_INT3]		= 7,
+	[IRQ_TNETV107X_TDM_CODECIF_EOT]		= 7,
+	[IRQ_TNETV107X_IMCOP_SQR_ARM]		= 7,
+	[IRQ_TNETV107X_USB0]			= 7,
+	[IRQ_TNETV107X_USB_CDMA]		= 7,
+	[IRQ_TNETV107X_LCD]			= 7,
+	[IRQ_TNETV107X_KEYPAD]			= 7,
+	[IRQ_TNETV107X_KEYPAD_FREE]		= 7,
+	[IRQ_TNETV107X_RNG]			= 7,
+	[IRQ_TNETV107X_PKA]			= 7,
+	[IRQ_TNETV107X_TDM0_TXDMA]		= 7,
+	[IRQ_TNETV107X_TDM0_RXDMA]		= 7,
+	[IRQ_TNETV107X_TDM0_TXMCSP]		= 7,
+	[IRQ_TNETV107X_TDM0_RXMCSP]		= 7,
+	[IRQ_TNETV107X_TDM1_RXMCSP]		= 7,
+	[IRQ_TNETV107X_SDIO1]			= 7,
+	[IRQ_TNETV107X_SDIO0]			= 7,
+	[IRQ_TNETV107X_TSC]			= 7,
+	[IRQ_TNETV107X_TS]			= 7,
+	[IRQ_TNETV107X_UART1]			= 7,
+	[IRQ_TNETV107X_MBX_LITE]		= 7,
+	[IRQ_TNETV107X_GPIO_INT00]		= 7,
+	[IRQ_TNETV107X_GPIO_INT01]		= 7,
+	[IRQ_TNETV107X_GPIO_INT02]		= 7,
+	[IRQ_TNETV107X_GPIO_INT03]		= 7,
+	[IRQ_TNETV107X_UART2]			= 7,
+	[IRQ_TNETV107X_UART2_DMATX]		= 7,
+	[IRQ_TNETV107X_UART2_DMARX]		= 7,
+	[IRQ_TNETV107X_IMCOP_IMX]		= 7,
+	[IRQ_TNETV107X_IMCOP_VLCD]		= 7,
+	[IRQ_TNETV107X_AES]			= 7,
+	[IRQ_TNETV107X_DES]			= 7,
+	[IRQ_TNETV107X_SHAMD5]			= 7,
+	[IRQ_TNETV107X_TPCC_ERR]		= 7,
+	[IRQ_TNETV107X_TPCC_PROT]		= 7,
+	[IRQ_TNETV107X_TPTC0_ERR]		= 7,
+	[IRQ_TNETV107X_TPTC1_ERR]		= 7,
+	[IRQ_TNETV107X_UART0_ERR]		= 7,
+	[IRQ_TNETV107X_UART1_ERR]		= 7,
+	[IRQ_TNETV107X_AEMIF_ERR]		= 7,
+	[IRQ_TNETV107X_DDR_ERR]			= 7,
+	[IRQ_TNETV107X_WDTARM_INT0]		= 7,
+	[IRQ_TNETV107X_MCDMA_ERR]		= 7,
+	[IRQ_TNETV107X_GPIO_ERR]		= 7,
+	[IRQ_TNETV107X_MPU_ADDR]		= 7,
+	[IRQ_TNETV107X_MPU_PROT]		= 7,
+	[IRQ_TNETV107X_IOPU_ADDR]		= 7,
+	[IRQ_TNETV107X_IOPU_PROT]		= 7,
+	[IRQ_TNETV107X_KEYPAD_ADDR_ERR]		= 7,
+	[IRQ_TNETV107X_WDT0_ADDR_ERR]		= 7,
+	[IRQ_TNETV107X_WDT1_ADDR_ERR]		= 7,
+	[IRQ_TNETV107X_CLKCTL_ADDR_ERR]		= 7,
+	[IRQ_TNETV107X_PLL_UNLOCK]		= 7,
+	[IRQ_TNETV107X_WDTDSP_INT0]		= 7,
+	[IRQ_TNETV107X_SEC_CTRL_VIOLATION]	= 7,
+	[IRQ_TNETV107X_KEY_MNG_VIOLATION]	= 7,
+	[IRQ_TNETV107X_PBIST_CPU]		= 7,
+	[IRQ_TNETV107X_WDTARM]			= 7,
+	[IRQ_TNETV107X_PSC]			= 7,
+	[IRQ_TNETV107X_MMC0]			= 7,
+	[IRQ_TNETV107X_MMC1]			= 7,
+};
+
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id tnetv107x_ids[] = {
+	{
+		.variant	= 0x0,
+		.part_no	= 0xb8a1,
+		.manufacturer	= 0x017,
+		.cpu_id		= DAVINCI_CPU_ID_TNETV107X,
+		.name		= "tnetv107x rev1.0",
+	},
+};
+
+static struct davinci_timer_instance tnetv107x_timer_instance[2] = {
+	{
+		.bottom_irq	= IRQ_TNETV107X_TIMER_0_TINT12,
+		.top_irq	= IRQ_TNETV107X_TIMER_0_TINT34,
+	},
+	{
+		.bottom_irq	= IRQ_TNETV107X_TIMER_1_TINT12,
+		.top_irq	= IRQ_TNETV107X_TIMER_1_TINT34,
+	},
+};
+
+static struct davinci_timer_info tnetv107x_timer_info = {
+	.timers		= tnetv107x_timer_instance,
+	.clockevent_id	= T0_BOT,
+	.clocksource_id	= T0_TOP,
+};
+
+/*
+ * TNETV107X platforms do not use the static mappings from Davinci
+ * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses,
+ * and changing IO_PHYS would break away from existing Davinci SOCs.
+ *
+ * The primary impact of the current model is that IO_ADDRESS() is not to be
+ * used to map registers on TNETV107X. With the exception of early boot code
+ * in tnetv107x_init() (where fixed maps are necessary), all other pieces of
+ * code absolutely _must_ use ioremap().
+ *
+ * In the following map, we reserve the top (highest address) 16K for mapping
+ * in interrupt controller registers. The remainder of the available space is
+ * mapped starting at physical address 0808:0000. All of the register areas
+ * accessed via fixed_ioremap() below must fall into one of these two
+ * segments.
+ */
+static struct map_desc tnetv107x_io_desc[] = {
+	{	/* EDMA */
+		.virtual	= IO_VIRT,
+		.pfn		= __phys_to_pfn(IO_PHYS),
+		.length		= SZ_1M,
+		.type		= MT_DEVICE
+	},
+	{	/* INTC */
+		.virtual	= IO_VIRT + SZ_1M,
+		.pfn		= __phys_to_pfn(TNETV107X_INTC_BASE),
+		.length		= SZ_1M,
+		.type		= MT_DEVICE
+	},
+	{	/* Most of the rest */
+		.virtual	= TNETV107X_IO_VIRT,
+		.pfn		= __phys_to_pfn(TNETV107X_IO_BASE),
+		.length		= IO_SIZE - SZ_2M,
+		.type		= MT_DEVICE
+	},
+};
+
+static struct davinci_soc_info tnetv107x_soc_info = {
+	.io_desc		= tnetv107x_io_desc,
+	.io_desc_num		= ARRAY_SIZE(tnetv107x_io_desc),
+	.ids			= tnetv107x_ids,
+	.ids_num		= ARRAY_SIZE(tnetv107x_ids),
+	.cpu_clks		= tnetv107x_clks,
+	.psc_bases		= psc_regs,
+	.psc_bases_num		= ARRAY_SIZE(psc_regs),
+	.pinmux_pins		= tnetv107x_pins,
+	.pinmux_pins_num	= ARRAY_SIZE(tnetv107x_pins),
+	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
+	.intc_irq_prios		= tnetv107x_irq_prios,
+	.intc_irq_num		= TNETV107X_N_CP_INTC_IRQ,
+	.timer_info		= &tnetv107x_timer_info,
+};
+
+static void __iomem *fixed_ioremap(unsigned long p, size_t size)
+{
+	struct map_desc *map = tnetv107x_soc_info.io_desc;
+	int i;
+
+	for (i = 0; i < tnetv107x_soc_info.io_desc_num; i++) {
+		unsigned long iophys = __pfn_to_phys(map[i].pfn);
+		unsigned long iosize = map[i].length;
+
+		if (p >= iophys && (p + size) <= (iophys + iosize))
+			return IOMEM(map[i].virtual + p - iophys);
+	}
+
+	panic("attempt to map invalid physical range %lx-%lx\n",
+			p, p + size);
+}
+
+void __init tnetv107x_init(void)
+{
+	void __iomem *tmp;
+	int i;
+
+	/*
+	 * Figure out virtual addresses for necessary peripherals, but do not
+	 * access any of these here. iotable_init() needs to happen for the
+	 * mappings to actually get setup
+	 */
+	tmp = fixed_ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K);
+	clk_ctrl_regs = tmp;
+
+	for (i = 0; i < N_PLLS; i++) {
+		sspll_regs[i] = tmp + sspll_regs_base[i];
+		pllctl_regs[i] = tmp + pllctl_regs_base[i];
+	}
+
+	tmp = fixed_ioremap(TNETV107X_PSC_BASE, SZ_4K);
+	psc_regs[0] = tmp;
+
+	tmp = fixed_ioremap(TNETV107X_CHIP_CFG_BASE, SZ_4K);
+	tnetv107x_soc_info.jtag_id_base	= tmp + 0x018;
+	tnetv107x_soc_info.pinmux_base	= tmp + 0x150;
+
+	tmp = fixed_ioremap(TNETV107X_INTC_BASE, SZ_16K);
+	tnetv107x_soc_info.intc_base	= tmp;
+
+	tmp = fixed_ioremap(TNETV107X_TIMER0_BASE, 0x100);
+	tnetv107x_timer_instance[0].base = tmp;
+
+	tmp = fixed_ioremap(TNETV107X_TIMER1_BASE, 0x100);
+	tnetv107x_timer_instance[1].base = tmp;
+
+	davinci_common_init(&tnetv107x_soc_info);
+}
+
+void __init tnetv107x_irq_init(void)
+{
+	struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+	cp_intc_init(soc_info->intc_base, soc_info->intc_irq_num,
+			soc_info->intc_irq_prios, intc_host_map);
+}
+
+static unsigned long clk_sspll_recalc(struct clk *clk)
+{
+	int		pll;
+	unsigned long	mult = 0, prediv = 1, postdiv = 1;
+	unsigned long	ref = OSC_FREQ_ONCHIP, ret;
+	u32		tmp;
+
+	if (WARN_ON(!clk->pll_data))
+		return clk->rate;
+
+	pll = clk->pll_data->num;
+
+	tmp = __raw_readl(&clk_ctrl_regs->pll_bypass);
+	if (!(tmp & bypass_mask[pll])) {
+		mult	= __raw_readl(&sspll_regs[pll]->mult_factor);
+		prediv	= __raw_readl(&sspll_regs[pll]->pre_div) + 1;
+		postdiv	= __raw_readl(&sspll_regs[pll]->post_div) + 1;
+	}
+
+	tmp = __raw_readl(pllctl_regs[pll] + PLLCTL);
+	if (tmp & PLLCTL_CLKMODE)
+		ref = pll_ext_freq[pll];
+
+	clk->pll_data->input_rate = ref;
+
+	tmp = __raw_readl(pllctl_regs[pll] + PLLCTL);
+	if (!(tmp & PLLCTL_PLLEN))
+		return ref;
+
+	ret = ref;
+	if (mult)
+		ret += ((unsigned long long)ref * mult) / 256;
+
+	ret /= (prediv * postdiv);
+
+	return ret;
+}
+
+static unsigned long clk_div_recalc(struct clk *clk)
+{
+	struct pll_data *pll;
+	unsigned long rate = clk->rate;
+	unsigned long div;
+
+	if (WARN_ON(!clk->parent))
+		return rate;
+
+	rate = clk->parent->rate;
+
+	/* Otherwise, the parent must be a PLL */
+	if (WARN_ON(!clk->parent->pll_data))
+		return rate;
+
+	pll = clk->parent->pll_data;
+
+	if (!clk->div_reg)
+		return rate;
+
+	div = __raw_readl(pllctl_regs[pll->num] + clk->div_reg);
+	if (div & PLLDIV_EN) {
+		div &= div_mask[pll->num];
+		rate /= (div + 1);
+	}
+
+	return rate;
+}
+
+static unsigned long clk_null_recalc(struct clk *clk)
+{
+	BUG_ON(!clk->parent);
+	return clk->parent->rate;
+}
