From patchwork Thu Apr 8 15:01:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thomas.koeller@baslerweb.com X-Patchwork-Id: 91287 Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o38F45op002340 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 8 Apr 2010 15:04:41 GMT Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o38F2IXN021749 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Apr 2010 10:02:18 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o38F2HBP024670; Thu, 8 Apr 2010 10:02:17 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 9A39B8062A; Thu, 8 Apr 2010 10:02:17 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp51.itg.ti.com (dflp51.itg.ti.com [128.247.22.94]) by linux.omap.com (Postfix) with ESMTP id AE7F780627 for ; Thu, 8 Apr 2010 10:02:13 -0500 (CDT) Received: from red.ext.ti.com (localhost [127.0.0.1]) by dflp51.itg.ti.com (8.13.7/8.13.7) with ESMTP id o38F2Dw1020153 for ; Thu, 8 Apr 2010 10:02:13 -0500 (CDT) Received: from psmtp.com (na3sys009amx165.postini.com [74.125.149.91]) by red.ext.ti.com (8.13.7/8.13.7) with SMTP id o38F2BJG011007 for ; Thu, 8 Apr 2010 10:02:12 -0500 Received: from source ([80.156.24.166]) by na3sys009amx165.postini.com ([74.125.148.10]) with SMTP; Thu, 08 Apr 2010 10:02:12 CDT Received: from unknown (HELO AHR075S.basler.corp) ([172.16.20.75]) by mail01-out.baslerweb.com with ESMTP; 08 Apr 2010 17:02:13 +0200 Received: from localhost.localdomain ([172.16.13.131]) by AHR075S.basler.corp with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Apr 2010 17:02:08 +0200 From: thomas.koeller@baslerweb.com To: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH 1/4] DM365: Make all SPI units SPI0..SPI4 available Date: Thu, 8 Apr 2010 17:01:55 +0200 Message-Id: <1270738918-30050-3-git-send-email-thomas.koeller@baslerweb.com> X-Mailer: git-send-email 1.7.0.3 In-Reply-To: <1270738918-30050-1-git-send-email-thomas.koeller@baslerweb.com> References: <1270738918-30050-1-git-send-email-thomas.koeller@baslerweb.com> X-OriginalArrivalTime: 08 Apr 2010 15:02:08.0214 (UTC) FILETIME=[756DBF60:01CAD72C] X-pstn-neptune: 0/0/0.00/0 X-pstn-levels: (S:99.90000/99.90000 CV:99.9000 FC:95.5390 LC:95.5390 R:95.9108 P:95.9108 M:97.0282 C:98.6951 ) X-pstn-settings: 2 (0.5000:0.5000) s cv gt3 gt2 gt1 r p m c X-pstn-addresses: from [db-null] X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Apr 2010 15:04:42 +0000 (UTC) diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index ab3b0e2..6797d3e 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -49,6 +49,8 @@ #include #include +#include "board_dm365_evm_resources.h" + /* have_imager() - Check if we have support for imager interface */ @@ -832,16 +834,39 @@ static struct spi_eeprom at25640 = { .flags = EE_ADDR2, }; -static struct spi_board_info dm365_evm_spi_info[] __initconst = { - { +static const struct spi_board_info + dm365_evm_spi_info_at25 __initconst = { .modalias = "at25", .platform_data = &at25640, .max_speed_hz = 20 * 1000 * 1000, /* at 3v3 */ .bus_num = 0, .chip_select = 0, .mode = SPI_MODE_0, - }, -}; + }; + +static struct dm365_spi_unit_desc + dm365_evm_spi_udesc_at25 = { + .spi_hwunit = 0, + .chipsel = BIT(0), + .irq = IRQ_SPI0, + .dma_tx_chan = DMA_CHAN_SPI0_TX, + .dma_rx_chan = DMA_CHAN_SPI0_RX, + .dma_evtq = DMA_EVQ_SPI0, + .pdata = { + .version = SPI_VERSION_1, + .num_chipselect = 2, + .clk_internal = 1, + .cs_hold = 1, + .intr_level = 0, + .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ + .use_dma = 1, /* when 1, value in poll_mode is ignored */ + .c2tdelay = 0, + .t2cdelay = 0 + } + }; + + + static __init void dm365_evm_init(void) { @@ -861,8 +886,8 @@ static __init void dm365_evm_init(void) dm365_init_rtc(); dm365_init_ks(&dm365evm_ks_data); - dm365_init_spi0(BIT(0), dm365_evm_spi_info, - ARRAY_SIZE(dm365_evm_spi_info)); + dm365_init_spi(&dm365_evm_spi_udesc_at25, 1, &dm365_evm_spi_info_at25); + return; } static __init void dm365_evm_irq_init(void) diff --git a/arch/arm/mach-davinci/board_dm365_evm_resources.h b/arch/arm/mach-davinci/board_dm365_evm_resources.h new file mode 100644 index 0000000..d9cfc6b --- /dev/null +++ b/arch/arm/mach-davinci/board_dm365_evm_resources.h @@ -0,0 +1,17 @@ +#ifndef _DAVINCI_EVM_RESOURCES_H +#define _DAVINCI_EVM_RESOURCES_H + +#include +#include + +/* IRQs */ +#define IRQ_SPI0 IRQ_DM365_SPIINT0_0 + +/* DMA channels */ +#define DMA_CHAN_SPI0_TX 16 +#define DMA_CHAN_SPI0_RX 17 + +/* DMA event queues */ +#define DMA_EVQ_SPI0 EVENTQ_3 + +#endif /* _DAVINCI_EVM_RESOURCES_H */ diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index ed6c9c7..023d708 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -616,72 +616,256 @@ EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false) #endif }; -static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); +static u64 dm365_spi_dma_mask = DMA_BIT_MASK(32); -static struct davinci_spi_platform_data dm365_spi0_pdata = { - .version = SPI_VERSION_1, - .num_chipselect = 2, - .clk_internal = 1, - .cs_hold = 1, - .intr_level = 0, - .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ - .use_dma = 1, /* when 1, value in poll_mode is ignored */ - .c2tdelay = 0, - .t2cdelay = 0, +enum dm365_spi_resource_index { + spirsrc_iomem, + spirsrc_irq, + spirsrc_rxdma, + spirsrc_txdma, + spirsrc_evqdma }; -static struct resource dm365_spi0_resources[] = { + +static struct resource dm365_spi_resources[spirsrc_evqdma + 1][5] = { { - .start = 0x01c66000, - .end = 0x01c667ff, - .flags = IORESOURCE_MEM, + [spirsrc_iomem] = { + .start = 0x01c66000, + .end = 0x01c667ff, + .flags = IORESOURCE_MEM, + }, + [spirsrc_irq] = { + .flags = IORESOURCE_IRQ, + }, + [spirsrc_rxdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, + }, + [spirsrc_txdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, + }, + [spirsrc_evqdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, + } }, { - .start = IRQ_DM365_SPIINT0_0, - .flags = IORESOURCE_IRQ, + [spirsrc_iomem] = { + .start = 0x01c66800, + .end = 0x01c66fff, + .flags = IORESOURCE_MEM, + }, + [spirsrc_irq] = { + .flags = IORESOURCE_IRQ, + }, + [spirsrc_rxdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, + }, + [spirsrc_txdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, + }, + [spirsrc_evqdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, + } }, { - .start = 17, - .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, + [spirsrc_iomem] = { + .start = 0x01c67800, + .end = 0x01c67fff, + .flags = IORESOURCE_MEM, + }, + [spirsrc_irq] = { + .flags = IORESOURCE_IRQ, + }, + [spirsrc_rxdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, + }, + [spirsrc_txdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, + }, + [spirsrc_evqdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, + } }, { - .start = 16, - .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, + [spirsrc_iomem] = { + .start = 0x01c68000, + .end = 0x01c687ff, + .flags = IORESOURCE_MEM, + }, + [spirsrc_irq] = { + .flags = IORESOURCE_IRQ, + }, + [spirsrc_rxdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, + }, + [spirsrc_txdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, + }, + [spirsrc_evqdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, + } }, { - .start = EVENTQ_3, - .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, + [spirsrc_iomem] = { + .start = 0x01c23000, + .end = 0x01c237ff, + .flags = IORESOURCE_MEM, + }, + [spirsrc_irq] = { + .flags = IORESOURCE_IRQ, + }, + [spirsrc_rxdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN, + }, + [spirsrc_txdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN, + }, + [spirsrc_evqdma] = { + .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q, + } + } +}; + +static struct platform_device dm365_spi_device[] = { + { + .name = "spi_davinci", + .id = 0, + .dev = { + .dma_mask = &dm365_spi_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(dm365_spi_resources[0]), + .resource = dm365_spi_resources[0] }, -}; - -static struct platform_device dm365_spi0_device = { - .name = "spi_davinci", - .id = 0, - .dev = { - .dma_mask = &dm365_spi0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &dm365_spi0_pdata, + { + .name = "spi_davinci", + .id = 1, + .dev = { + .dma_mask = &dm365_spi_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(dm365_spi_resources[1]), + .resource = dm365_spi_resources[1] + }, + { + .name = "spi_davinci", + .id = 2, + .dev = { + .dma_mask = &dm365_spi_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(dm365_spi_resources[2]), + .resource = dm365_spi_resources[2] + }, + { + .name = "spi_davinci", + .id = 3, + .dev = { + .dma_mask = &dm365_spi_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(dm365_spi_resources[3]), + .resource = dm365_spi_resources[3] }, - .num_resources = ARRAY_SIZE(dm365_spi0_resources), - .resource = dm365_spi0_resources, + { + .name = "spi_davinci", + .id = 4, + .dev = { + .dma_mask = &dm365_spi_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(dm365_spi_resources[4]), + .resource = dm365_spi_resources[4] + } +}; + +struct dm365_spi_pins { + int sclk; + int sdi; + int sdo; + int sdena0; + int sdena1; +}; + +static const struct dm365_spi_pins dm365_spi_pinmap[] __initconst = { + { + .sclk = DM365_SPI0_SCLK, + .sdi = DM365_SPI0_SDI, + .sdo = DM365_SPI0_SDO, + .sdena0 = DM365_SPI0_SDENA0, + .sdena1 = DM365_SPI0_SDENA1 + }, + { + .sclk = DM365_SPI1_SCLK, + .sdi = DM365_SPI1_SDI, + .sdo = DM365_SPI1_SDO, + .sdena0 = DM365_SPI1_SDENA0, + .sdena1 = DM365_SPI1_SDENA1 + }, + { + .sclk = DM365_SPI2_SCLK, + .sdi = DM365_SPI2_SDI, + .sdo = DM365_SPI2_SDO, + .sdena0 = DM365_SPI2_SDENA0, + .sdena1 = DM365_SPI2_SDENA1 + }, + { + .sclk = DM365_SPI3_SCLK, + .sdi = DM365_SPI3_SDI, + .sdo = DM365_SPI3_SDO, + .sdena0 = DM365_SPI3_SDENA0, + .sdena1 = DM365_SPI3_SDENA1 + }, + { + .sclk = DM365_SPI4_SCLK, + .sdi = DM365_SPI4_SDI, + .sdo = DM365_SPI4_SDO, + .sdena0 = DM365_SPI4_SDENA0, + .sdena1 = DM365_SPI4_SDENA1 + } }; -void __init dm365_init_spi0(unsigned chipselect_mask, - struct spi_board_info *info, unsigned len) +void __init dm365_init_spi(struct dm365_spi_unit_desc *unit, + unsigned int ninfo, + const struct spi_board_info *info) { - davinci_cfg_reg(DM365_SPI0_SCLK); - davinci_cfg_reg(DM365_SPI0_SDI); - davinci_cfg_reg(DM365_SPI0_SDO); + int err; + const unsigned int hwunit = unit->spi_hwunit; + const struct dm365_spi_pins * const pins = &dm365_spi_pinmap[hwunit]; + struct platform_device * const pdev = &dm365_spi_device[hwunit]; + struct davinci_spi_platform_data * const pdata = &unit->pdata; - /* not all slaves will be wired up */ - if (chipselect_mask & BIT(0)) - davinci_cfg_reg(DM365_SPI0_SDENA0); - if (chipselect_mask & BIT(1)) - davinci_cfg_reg(DM365_SPI0_SDENA1); - - spi_register_board_info(info, len); + davinci_cfg_reg(pins->sclk); + davinci_cfg_reg(pins->sdi); + davinci_cfg_reg(pins->sdo); - platform_device_register(&dm365_spi0_device); + /* not all slaves will be wired up */ + if (unit->chipsel & BIT(0)) + davinci_cfg_reg(pins->sdena0); + if (unit->chipsel & BIT(1)) + davinci_cfg_reg(pins->sdena1); + + pdev->dev.platform_data = pdata; + + pdev->resource[spirsrc_irq].start = + pdev->resource[spirsrc_irq].end = unit->irq; + pdev->resource[spirsrc_rxdma].start = + pdev->resource[spirsrc_rxdma].end = unit->dma_rx_chan; + pdev->resource[spirsrc_txdma].start = + pdev->resource[spirsrc_txdma].end = unit->dma_tx_chan; + pdev->resource[spirsrc_evqdma].start = + pdev->resource[spirsrc_evqdma].end = unit->dma_evtq; + + pr_debug("Creating SPI%u: irq = %u, dma_rx = %u, dma_tx = %u, " + "dma_evq = %u", + hwunit, unit->irq, unit->dma_rx_chan, unit->dma_tx_chan, + unit->dma_evtq); + + err = platform_device_register(pdev); + if (unlikely(err)) + pr_err("Failed to create platform device for SPI%u - error %d", + hwunit, err); + + spi_register_board_info(info, ninfo); } diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h index 44b0cc6..3d2a823 100644 --- a/arch/arm/mach-davinci/include/mach/dm365.h +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -19,6 +19,7 @@ #include #include #include +#include #define DM365_EMAC_BASE (0x01D07000) #define DM365_EMAC_CNTRL_OFFSET (0x0000) @@ -38,8 +39,19 @@ void __init dm365_init_rtc(void); void __init dm365_init_ks(struct davinci_ks_platform_data *pdata); void dm365_set_vpfe_config(struct vpfe_config *cfg); +struct dm365_spi_unit_desc { + unsigned int spi_hwunit; + unsigned int chipsel; + unsigned int irq; + unsigned int dma_tx_chan; + unsigned int dma_rx_chan; + unsigned int dma_evtq; + struct davinci_spi_platform_data pdata; +}; + struct spi_board_info; -void dm365_init_spi0(unsigned chipselect_mask, - struct spi_board_info *info, unsigned len); +void dm365_init_spi(struct dm365_spi_unit_desc *unit, + unsigned int ninfo, + const struct spi_board_info *info); #endif /* __ASM_ARCH_DM365_H */