From patchwork Mon Apr 12 21:15:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 92092 Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3CLJC8q003342 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Mon, 12 Apr 2010 21:19:52 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3CLI02V025073 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 12 Apr 2010 16:18:00 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3CLHwJk016272; Mon, 12 Apr 2010 16:17:58 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 98BEF806C5; Mon, 12 Apr 2010 16:16:45 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dlep35.itg.ti.com (dlep35.itg.ti.com [157.170.170.118]) by linux.omap.com (Postfix) with ESMTP id 8D9218062B for ; Mon, 12 Apr 2010 16:15:40 -0500 (CDT) Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3CLFb40010884; Mon, 12 Apr 2010 16:15:37 -0500 (CDT) Received: from gtrgwdeb (gtrgwdeb.telogy.design.ti.com [158.218.102.24]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o3CLFaZ20716; Mon, 12 Apr 2010 16:15:36 -0500 (CDT) Received: by gtrgwdeb (Postfix, from userid 39959) id E3F651E2932; Mon, 12 Apr 2010 17:15:35 -0400 (EDT) From: Cyril Chemparathy To: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH 5/8] Davinci: gpio - struct renames Date: Mon, 12 Apr 2010 17:15:30 -0400 Message-Id: <1271106933-13911-6-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1271106933-13911-5-git-send-email-cyril@ti.com> References: <1271106933-13911-1-git-send-email-cyril@ti.com> <1271106933-13911-2-git-send-email-cyril@ti.com> <1271106933-13911-3-git-send-email-cyril@ti.com> <1271106933-13911-4-git-send-email-cyril@ti.com> <1271106933-13911-5-git-send-email-cyril@ti.com> Cc: sshtylyov@mvista.com X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 12 Apr 2010 21:19:52 +0000 (UTC) diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index bb55f41..58a6fd5 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -22,28 +22,22 @@ static DEFINE_SPINLOCK(gpio_lock); -struct davinci_gpio { - struct gpio_chip chip; - struct gpio_controller __iomem *regs; - int irq_base; -}; - #define chip2controller(chip) \ - container_of(chip, struct davinci_gpio, chip) + container_of(chip, struct davinci_gpio_controller, chip) -static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; +static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; /* create a non-inlined version */ -static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio) +static struct davinci_gpio_regs __iomem __init *gpio2controller(unsigned gpio) { return __gpio_to_controller(gpio); } -static inline struct gpio_controller __iomem *irq2controller(int irq) +static inline struct davinci_gpio_regs __iomem *irq2controller(int irq) { - struct gpio_controller __iomem *g; + struct davinci_gpio_regs __iomem *g; - g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq); + g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); return g; } @@ -60,8 +54,8 @@ static int __init davinci_gpio_irq_setup(void); static inline int __davinci_direction(struct gpio_chip *chip, unsigned offset, bool out) { - struct davinci_gpio *d = chip2controller(chip); - struct gpio_controller __iomem *g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; u32 temp; spin_lock(&gpio_lock); @@ -96,8 +90,8 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) */ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) { - struct davinci_gpio *d = chip2controller(chip); - struct gpio_controller __iomem *g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; return (1 << offset) & __raw_readl(&g->in_data); } @@ -108,8 +102,8 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - struct davinci_gpio *d = chip2controller(chip); - struct gpio_controller __iomem *g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); } @@ -171,7 +165,7 @@ pure_initcall(davinci_gpio_setup); static void gpio_irq_disable(unsigned irq) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = (u32) get_irq_data(irq); __raw_writel(mask, &g->clr_falling); @@ -180,7 +174,7 @@ static void gpio_irq_disable(unsigned irq) static void gpio_irq_enable(unsigned irq) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = (u32) get_irq_data(irq); unsigned status = irq_desc[irq].status; @@ -196,7 +190,7 @@ static void gpio_irq_enable(unsigned irq) static int gpio_irq_type(unsigned irq, unsigned trigger) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = (u32) get_irq_data(irq); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) @@ -225,7 +219,7 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = 0xffff; /* we only care about one bank */ @@ -263,7 +257,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) { - struct davinci_gpio *d = chip2controller(chip); + struct davinci_gpio_controller *d = chip2controller(chip); if (d->irq_base >= 0) return d->irq_base + offset; @@ -286,7 +280,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = (u32) get_irq_data(irq); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) @@ -315,7 +309,7 @@ static int __init davinci_gpio_irq_setup(void) u32 binten = 0; unsigned ngpio, bank_irq; struct davinci_soc_info *soc_info = &davinci_soc_info; - struct gpio_controller __iomem *g; + struct davinci_gpio_regs __iomem *g; ngpio = soc_info->gpio_num; diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index 0099e6e..bdab001 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -45,7 +45,7 @@ /* Convert GPIO signal to GPIO pin number */ #define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) -struct gpio_controller { +struct davinci_gpio_regs { u32 dir; u32 out_data; u32 set_data; @@ -58,6 +58,12 @@ struct gpio_controller { u32 intstat; }; +struct davinci_gpio_controller { + struct davinci_gpio_regs __iomem *regs; + struct gpio_chip chip; + int irq_base; +}; + /* The __gpio_to_controller() and __gpio_mask() functions inline to constants * with constant parameters; or in outlined code they execute at runtime. * @@ -67,7 +73,7 @@ struct gpio_controller { * * These are NOT part of the cross-platform GPIO interface */ -static inline struct gpio_controller __iomem * +static inline struct davinci_gpio_regs __iomem * __gpio_to_controller(unsigned gpio) { void __iomem *ptr; @@ -102,7 +108,7 @@ static inline u32 __gpio_mask(unsigned gpio) static inline void gpio_set_value(unsigned gpio, int value) { if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) { - struct gpio_controller __iomem *g; + struct davinci_gpio_regs __iomem *g; u32 mask; g = __gpio_to_controller(gpio); @@ -128,7 +134,7 @@ static inline void gpio_set_value(unsigned gpio, int value) */ static inline int gpio_get_value(unsigned gpio) { - struct gpio_controller __iomem *g; + struct davinci_gpio_regs __iomem *g; if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO) return __gpio_get_value(gpio);