From patchwork Wed Apr 14 18:44:56 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 92466 Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3EIo9I5002183 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Wed, 14 Apr 2010 18:50:45 GMT Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3EIlqOv008209 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 14 Apr 2010 13:47:52 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3EIlpc7029128; Wed, 14 Apr 2010 13:47:51 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id D46B380665; Wed, 14 Apr 2010 13:47:07 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dlep34.itg.ti.com (dlep34.itg.ti.com [157.170.170.115]) by linux.omap.com (Postfix) with ESMTP id 24C6580626 for ; Wed, 14 Apr 2010 13:45:11 -0500 (CDT) Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3EIj8Kk006234; Wed, 14 Apr 2010 13:45:08 -0500 (CDT) Received: from gtrgwdeb (gtrgwdeb.telogy.design.ti.com [158.218.102.24]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o3EIj7Z05956; Wed, 14 Apr 2010 13:45:07 -0500 (CDT) Received: by gtrgwdeb (Postfix, from userid 39959) id 2018E1E0668; Wed, 14 Apr 2010 14:45:05 -0400 (EDT) From: Cyril Chemparathy To: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH v3 10/16] Davinci: gpio - fine grained locking Date: Wed, 14 Apr 2010 14:44:56 -0400 Message-Id: <1271270702-28307-11-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1271270702-28307-10-git-send-email-cyril@ti.com> References: <1271270702-28307-1-git-send-email-cyril@ti.com> <1271270702-28307-2-git-send-email-cyril@ti.com> <1271270702-28307-3-git-send-email-cyril@ti.com> <1271270702-28307-4-git-send-email-cyril@ti.com> <1271270702-28307-5-git-send-email-cyril@ti.com> <1271270702-28307-6-git-send-email-cyril@ti.com> <1271270702-28307-7-git-send-email-cyril@ti.com> <1271270702-28307-8-git-send-email-cyril@ti.com> <1271270702-28307-9-git-send-email-cyril@ti.com> <1271270702-28307-10-git-send-email-cyril@ti.com> Cc: sshtylyov@mvista.com X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 14 Apr 2010 18:50:46 +0000 (UTC) diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 419254a..60e59fc 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -33,8 +33,6 @@ struct davinci_gpio_regs { u32 intstat; }; -static DEFINE_SPINLOCK(gpio_lock); - #define chip2controller(chip) \ container_of(chip, struct davinci_gpio_controller, chip) @@ -83,13 +81,14 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) { struct davinci_gpio_controller *d = chip2controller(chip); struct davinci_gpio_regs __iomem *g = d->regs; + unsigned long flags; u32 temp; - spin_lock(&gpio_lock); + spin_lock_irqsave(&d->lock, flags); temp = __raw_readl(&g->dir); temp |= (1 << offset); __raw_writel(temp, &g->dir); - spin_unlock(&gpio_lock); + spin_unlock_irqrestore(&d->lock, flags); return 0; } @@ -114,15 +113,16 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) { struct davinci_gpio_controller *d = chip2controller(chip); struct davinci_gpio_regs __iomem *g = d->regs; + unsigned long flags; u32 temp; u32 mask = 1 << offset; - spin_lock(&gpio_lock); + spin_lock_irqsave(&d->lock, flags); temp = __raw_readl(&g->dir); temp &= ~mask; __raw_writel(mask, value ? &g->set_data : &g->clr_data); __raw_writel(temp, &g->dir); - spin_unlock(&gpio_lock); + spin_unlock_irqrestore(&d->lock, flags); return 0; } @@ -175,6 +175,8 @@ static int __init davinci_gpio_setup(void) if (chips[i].chip.ngpio > 32) chips[i].chip.ngpio = 32; + spin_lock_init(&chips[i].lock); + regs = gpio2regs(base); chips[i].regs = regs; chips[i].set_data = ®s->set_data; diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index 9a71a26..e3cbef1 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -14,6 +14,8 @@ #define __DAVINCI_GPIO_H #include +#include + #include #include @@ -51,6 +53,7 @@ enum davinci_gpio_type { struct davinci_gpio_controller { struct gpio_chip chip; + spinlock_t lock; int irq_base; void __iomem *regs; void __iomem *set_data;