From patchwork Fri Apr 23 17:56:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 94729 Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3NI0AeB024930 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 23 Apr 2010 18:00:46 GMT Received: from dlep35.itg.ti.com ([157.170.170.118]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3NHwWEh000983 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 23 Apr 2010 12:58:32 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3NHwR2g027530; Fri, 23 Apr 2010 12:58:31 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id B64908062F; Fri, 23 Apr 2010 12:58:17 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dlep34.itg.ti.com (dlep34.itg.ti.com [157.170.170.115]) by linux.omap.com (Postfix) with ESMTP id A37518062A for ; Fri, 23 Apr 2010 12:57:11 -0500 (CDT) Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3NHv8uE013026; Fri, 23 Apr 2010 12:57:08 -0500 (CDT) Received: from gtrgwdeb (gtrgwdeb.telogy.design.ti.com [158.218.102.24]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o3NHv8Z01766; Fri, 23 Apr 2010 12:57:08 -0500 (CDT) Received: by gtrgwdeb (Postfix, from userid 39959) id B100F1E24FB; Fri, 23 Apr 2010 13:57:07 -0400 (EDT) From: Cyril Chemparathy To: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH v4 02/13] Davinci: gpio - minor cleanup Date: Fri, 23 Apr 2010 13:56:53 -0400 Message-Id: <1272045424-19240-3-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1272045424-19240-2-git-send-email-cyril@ti.com> References: <1272045424-19240-1-git-send-email-cyril@ti.com> <1272045424-19240-2-git-send-email-cyril@ti.com> Cc: sshtylyov@mvista.com X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 23 Apr 2010 18:00:48 +0000 (UTC) diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 5476ad1..93f7c68 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -28,6 +28,9 @@ struct davinci_gpio { int irq_base; }; +#define chip2controller(chip) \ + container_of(chip, struct davinci_gpio, chip) + static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; /* create a non-inlined version */ @@ -54,21 +57,39 @@ static int __init davinci_gpio_irq_setup(void); * needed, and enable the GPIO clock. */ -static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) +static inline int __davinci_direction(struct gpio_chip *chip, + unsigned offset, bool out, int value) { - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); + struct davinci_gpio *d = chip2controller(chip); struct gpio_controller __iomem *g = d->regs; u32 temp; + u32 mask = 1 << offset; spin_lock(&gpio_lock); temp = __raw_readl(&g->dir); - temp |= (1 << offset); + if (out) { + temp &= ~mask; + __raw_writel(mask, value ? &g->set_data : &g->clr_data); + } else { + temp |= mask; + } __raw_writel(temp, &g->dir); spin_unlock(&gpio_lock); return 0; } +static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) +{ + return __davinci_direction(chip, offset, false, 0); +} + +static int +davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) +{ + return __davinci_direction(chip, offset, true, value); +} + /* * Read the pin's value (works even if it's set up as output); * returns zero/nonzero. @@ -78,36 +99,19 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) */ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) { - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); + struct davinci_gpio *d = chip2controller(chip); struct gpio_controller __iomem *g = d->regs; return (1 << offset) & __raw_readl(&g->in_data); } -static int -davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) -{ - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); - struct gpio_controller __iomem *g = d->regs; - u32 temp; - u32 mask = 1 << offset; - - spin_lock(&gpio_lock); - temp = __raw_readl(&g->dir); - temp &= ~mask; - __raw_writel(mask, value ? &g->set_data : &g->clr_data); - __raw_writel(temp, &g->dir); - spin_unlock(&gpio_lock); - return 0; -} - /* * Assuming the pin is muxed as a gpio output, set its output value. */ static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); + struct davinci_gpio *d = chip2controller(chip); struct gpio_controller __iomem *g = d->regs; __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); @@ -262,7 +266,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) { - struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); + struct davinci_gpio *d = chip2controller(chip); if (d->irq_base >= 0) return d->irq_base + offset;