@@ -32,6 +32,6 @@ obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o
-obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
+obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o dm365_spi.o
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
@@ -49,6 +49,8 @@
#include <media/tvp7002.h>
#include <media/davinci/videohd.h>
+#include "spi.h"
+
/* have_imager() - Check if we have support for imager interface */
@@ -337,18 +339,18 @@ static struct i2c_driver pca9543a_driver = {
static void dm365evm_reset_imager(int rst)
{
u8 val;
-
+
/* Reset bit6 of CPLD_IMG_DIR2 */
val = __raw_readb(cpld + CPLD_IMG_DIR2) & ~BIT(6);
- __raw_writeb(val, (cpld + CPLD_IMG_DIR2));
+ __raw_writeb(val, (cpld + CPLD_IMG_DIR2));
/* Set bit5 of CPLD_IMG_MUX5 */
val = __raw_readb(cpld + CPLD_IMG_MUX5) | BIT(5);
- __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
+ __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
/* Reset bit 0 of CPLD_IMG_MUX5 */
val = __raw_readb(cpld + CPLD_IMG_MUX5) & ~BIT(0);
- __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
+ __raw_writeb(val, (cpld + CPLD_IMG_MUX5));
/**
* Configure GPIO40 to be output and high. This has dependency on MMC1
@@ -375,7 +377,7 @@ static int dm365evm_enable_pca9543a(int en)
.buf = &val,
};
- printk("dm365evm_enable_pca9543a\n");
+ printk("dm365evm_enable_pca9543a\n");
if (!en)
val = 0;
@@ -385,7 +387,7 @@ static int dm365evm_enable_pca9543a(int en)
msg.addr = pca9543a->addr;
/* turn i2c switch, pca9543a, on/off */
status = i2c_transfer(pca9543a->adapter, &msg, 1);
- printk("dm365evm_enable_pca9543a, status = %d\n", status);
+ printk("dm365evm_enable_pca9543a, status = %d\n", status);
return status;
return 0;
}
@@ -832,7 +834,7 @@ static struct spi_eeprom at25640 = {
.flags = EE_ADDR2,
};
-static struct spi_board_info dm365_evm_spi_info[] __initconst = {
+static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
{
.modalias = "at25",
.platform_data = &at25640,
@@ -840,9 +842,32 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = {
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
- },
+ }
+};
+
+static struct davinci_spi_unit_desc dm365_evm_spi_udesc_at25 = {
+ .spi_hwunit = 0,
+ .chipsel = BIT(0),
+ .irq = IRQ_DM365_SPIINT0_0,
+ .dma_tx_chan = 16,
+ .dma_rx_chan = 17,
+ .dma_evtq = EVENTQ_3,
+ .pdata = {
+ .version = SPI_VERSION_1,
+ .num_chipselect = 2,
+ .clk_internal = 1,
+ .cs_hold = 1,
+ .intr_level = 0,
+ .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
+ .use_dma = 1, /* when 1, value in poll_mode is ignored */
+ .c2tdelay = 0,
+ .t2cdelay = 0
+ }
};
+
+
+
static __init void dm365_evm_init(void)
{
evm_init_i2c();
@@ -861,8 +886,10 @@ static __init void dm365_evm_init(void)
dm365_init_rtc();
dm365_init_ks(&dm365evm_ks_data);
- dm365_init_spi0(BIT(0), dm365_evm_spi_info,
- ARRAY_SIZE(dm365_evm_spi_info));
+ davinci_init_spi(&dm365_evm_spi_udesc_at25,
+ ARRAY_SIZE(dm365_evm_spi_info),
+ dm365_evm_spi_info);
+ return;
}
static __init void dm365_evm_irq_init(void)
@@ -616,74 +616,6 @@ EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
#endif
};
-static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
-
-static struct davinci_spi_platform_data dm365_spi0_pdata = {
- .version = SPI_VERSION_1,
- .num_chipselect = 2,
- .clk_internal = 1,
- .cs_hold = 1,
- .intr_level = 0,
- .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
- .use_dma = 1, /* when 1, value in poll_mode is ignored */
- .c2tdelay = 0,
- .t2cdelay = 0,
-};
-
-static struct resource dm365_spi0_resources[] = {
- {
- .start = 0x01c66000,
- .end = 0x01c667ff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_DM365_SPIINT0_0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = 17,
- .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
- },
- {
- .start = 16,
- .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
- },
- {
- .start = EVENTQ_3,
- .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
- },
-};
-
-static struct platform_device dm365_spi0_device = {
- .name = "spi_davinci",
- .id = 0,
- .dev = {
- .dma_mask = &dm365_spi0_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dm365_spi0_pdata,
- },
- .num_resources = ARRAY_SIZE(dm365_spi0_resources),
- .resource = dm365_spi0_resources,
-};
-
-void __init dm365_init_spi0(unsigned chipselect_mask,
- struct spi_board_info *info, unsigned len)
-{
- davinci_cfg_reg(DM365_SPI0_SCLK);
- davinci_cfg_reg(DM365_SPI0_SDI);
- davinci_cfg_reg(DM365_SPI0_SDO);
-
- /* not all slaves will be wired up */
- if (chipselect_mask & BIT(0))
- davinci_cfg_reg(DM365_SPI0_SDENA0);
- if (chipselect_mask & BIT(1))
- davinci_cfg_reg(DM365_SPI0_SDENA1);
-
- spi_register_board_info(info, len);
-
- platform_device_register(&dm365_spi0_device);
-}
-
/* IPIPEIF device configuration */
static u64 dm365_ipipeif_dma_mask = DMA_BIT_MASK(32);
new file mode 100644
@@ -0,0 +1,276 @@
+/*
+ * TI DaVinci DM3xx SPI setup
+ *
+ * Copyright (C) 2010 Basler Vision Technologies AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/ioport.h>
+#include <linux/spi/spi.h>
+#include <mach/mux.h>
+
+#include "spi.h"
+
+static u64 davinci_spi_dma_mask = DMA_BIT_MASK(32);
+
+enum davinci_spi_resource_index {
+ spirsrc_iomem,
+ spirsrc_irq,
+ spirsrc_rxdma,
+ spirsrc_txdma,
+ spirsrc_evqdma
+};
+
+
+static struct resource davinci_spi_resources[spirsrc_evqdma + 1][5] = {
+ {
+ [spirsrc_iomem] = {
+ .start = 0x01c66000,
+ .end = 0x01c667ff,
+ .flags = IORESOURCE_MEM,
+ },
+ [spirsrc_irq] = {
+ .flags = IORESOURCE_IRQ,
+ },
+ [spirsrc_rxdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+ },
+ [spirsrc_txdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+ },
+ [spirsrc_evqdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+ }
+ },
+ {
+ [spirsrc_iomem] = {
+ .start = 0x01c66800,
+ .end = 0x01c66fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [spirsrc_irq] = {
+ .flags = IORESOURCE_IRQ,
+ },
+ [spirsrc_rxdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+ },
+ [spirsrc_txdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+ },
+ [spirsrc_evqdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+ }
+ },
+ {
+ [spirsrc_iomem] = {
+ .start = 0x01c67800,
+ .end = 0x01c67fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [spirsrc_irq] = {
+ .flags = IORESOURCE_IRQ,
+ },
+ [spirsrc_rxdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+ },
+ [spirsrc_txdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+ },
+ [spirsrc_evqdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+ }
+ },
+ {
+ [spirsrc_iomem] = {
+ .start = 0x01c68000,
+ .end = 0x01c687ff,
+ .flags = IORESOURCE_MEM,
+ },
+ [spirsrc_irq] = {
+ .flags = IORESOURCE_IRQ,
+ },
+ [spirsrc_rxdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+ },
+ [spirsrc_txdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+ },
+ [spirsrc_evqdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+ }
+ },
+ {
+ [spirsrc_iomem] = {
+ .start = 0x01c23000,
+ .end = 0x01c237ff,
+ .flags = IORESOURCE_MEM,
+ },
+ [spirsrc_irq] = {
+ .flags = IORESOURCE_IRQ,
+ },
+ [spirsrc_rxdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_RX_CHAN,
+ },
+ [spirsrc_txdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_TX_CHAN,
+ },
+ [spirsrc_evqdma] = {
+ .flags = IORESOURCE_DMA | IORESOURCE_DMA_EVENT_Q,
+ }
+ }
+};
+
+static struct platform_device davinci_spi_device[] = {
+ {
+ .name = "spi_davinci",
+ .id = 0,
+ .dev = {
+ .dma_mask = &davinci_spi_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(davinci_spi_resources[0]),
+ .resource = davinci_spi_resources[0]
+ },
+ {
+ .name = "spi_davinci",
+ .id = 1,
+ .dev = {
+ .dma_mask = &davinci_spi_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(davinci_spi_resources[1]),
+ .resource = davinci_spi_resources[1]
+ },
+ {
+ .name = "spi_davinci",
+ .id = 2,
+ .dev = {
+ .dma_mask = &davinci_spi_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(davinci_spi_resources[2]),
+ .resource = davinci_spi_resources[2]
+ },
+ {
+ .name = "spi_davinci",
+ .id = 3,
+ .dev = {
+ .dma_mask = &davinci_spi_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(davinci_spi_resources[3]),
+ .resource = davinci_spi_resources[3]
+ },
+ {
+ .name = "spi_davinci",
+ .id = 4,
+ .dev = {
+ .dma_mask = &davinci_spi_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(davinci_spi_resources[4]),
+ .resource = davinci_spi_resources[4]
+ }
+};
+
+struct davinci_spi_pins {
+ int sclk;
+ int sdi;
+ int sdo;
+ int sdena0;
+ int sdena1;
+};
+
+static const struct davinci_spi_pins davinci_spi_pinmap[] __initconst = {
+ {
+ .sclk = DM365_SPI0_SCLK,
+ .sdi = DM365_SPI0_SDI,
+ .sdo = DM365_SPI0_SDO,
+ .sdena0 = DM365_SPI0_SDENA0,
+ .sdena1 = DM365_SPI0_SDENA1
+ },
+ {
+ .sclk = DM365_SPI1_SCLK,
+ .sdi = DM365_SPI1_SDI,
+ .sdo = DM365_SPI1_SDO,
+ .sdena0 = DM365_SPI1_SDENA0,
+ .sdena1 = DM365_SPI1_SDENA1
+ },
+ {
+ .sclk = DM365_SPI2_SCLK,
+ .sdi = DM365_SPI2_SDI,
+ .sdo = DM365_SPI2_SDO,
+ .sdena0 = DM365_SPI2_SDENA0,
+ .sdena1 = DM365_SPI2_SDENA1
+ },
+ {
+ .sclk = DM365_SPI3_SCLK,
+ .sdi = DM365_SPI3_SDI,
+ .sdo = DM365_SPI3_SDO,
+ .sdena0 = DM365_SPI3_SDENA0,
+ .sdena1 = DM365_SPI3_SDENA1
+ },
+ {
+ .sclk = DM365_SPI4_SCLK,
+ .sdi = DM365_SPI4_SDI,
+ .sdo = DM365_SPI4_SDO,
+ .sdena0 = DM365_SPI4_SDENA0,
+ .sdena1 = DM365_SPI4_SDENA1
+ }
+};
+
+void __init davinci_init_spi(struct davinci_spi_unit_desc *unit,
+ unsigned int ninfo,
+ const struct spi_board_info *info)
+{
+ int err;
+ const unsigned int hwunit = unit->spi_hwunit;
+ const struct davinci_spi_pins * const pins = &davinci_spi_pinmap[hwunit];
+ struct platform_device * const pdev = &davinci_spi_device[hwunit];
+ struct davinci_spi_platform_data * const pdata = &unit->pdata;
+
+ davinci_cfg_reg(pins->sclk);
+ davinci_cfg_reg(pins->sdi);
+ davinci_cfg_reg(pins->sdo);
+
+ /* not all slaves will be wired up */
+ if (unit->chipsel & BIT(0))
+ davinci_cfg_reg(pins->sdena0);
+ if (unit->chipsel & BIT(1))
+ davinci_cfg_reg(pins->sdena1);
+
+ pdev->dev.platform_data = pdata;
+
+ pdev->resource[spirsrc_irq].start =
+ pdev->resource[spirsrc_irq].end = unit->irq;
+ pdev->resource[spirsrc_rxdma].start =
+ pdev->resource[spirsrc_rxdma].end = unit->dma_rx_chan;
+ pdev->resource[spirsrc_txdma].start =
+ pdev->resource[spirsrc_txdma].end = unit->dma_tx_chan;
+ pdev->resource[spirsrc_evqdma].start =
+ pdev->resource[spirsrc_evqdma].end = unit->dma_evtq;
+
+ pr_debug("Creating SPI%u: irq = %u, dma_rx = %u, dma_tx = %u, "
+ "dma_evq = %u",
+ hwunit, unit->irq, unit->dma_rx_chan, unit->dma_tx_chan,
+ unit->dma_evtq);
+
+ err = platform_device_register(pdev);
+ if (unlikely(err))
+ pr_err("Failed to create platform device for SPI%u - error %d",
+ hwunit, err);
+
+ spi_register_board_info(info, ninfo);
+}
+
+
@@ -19,6 +19,7 @@
#include <mach/emac.h>
#include <mach/asp.h>
#include <mach/keyscan.h>
+#include <mach/spi.h>
#define DM365_EMAC_BASE (0x01D07000)
#define DM365_EMAC_CNTRL_OFFSET (0x0000)
@@ -38,8 +39,4 @@ void __init dm365_init_rtc(void);
void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
void dm365_set_vpfe_config(struct vpfe_config *cfg);
-struct spi_board_info;
-void dm365_init_spi0(unsigned chipselect_mask,
- struct spi_board_info *info, unsigned len);
-
#endif /* __ASM_ARCH_DM365_H */
new file mode 100644
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010 Basler Vision Technologies AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_DAVINCI_SPI_H
+#define __MACH_DAVINCI_SPI_H
+
+#include <mach/spi.h>
+
+struct davinci_spi_unit_desc {
+ unsigned int spi_hwunit;
+ unsigned int chipsel;
+ unsigned int irq;
+ unsigned int dma_tx_chan;
+ unsigned int dma_rx_chan;
+ unsigned int dma_evtq;
+ struct davinci_spi_platform_data pdata;
+};
+
+struct spi_board_info;
+
+void __init davinci_init_spi(struct davinci_spi_unit_desc *unit,
+ unsigned int ninfo,
+ const struct spi_board_info *info);
+
+
+#endif /* __MACH_DAVINCI_SPI_H */