From patchwork Tue Mar 15 21:08:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Gardiner X-Patchwork-Id: 637321 Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p2FLB6sb015475 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 15 Mar 2011 21:11:27 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p2FL8t3r004055 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 15 Mar 2011 16:08:55 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id p2FL8sEt011940; Tue, 15 Mar 2011 16:08:54 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 4BFAE80627; Tue, 15 Mar 2011 15:08:54 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp51.itg.ti.com (dflp51.itg.ti.com [128.247.22.94]) by linux.omap.com (Postfix) with ESMTP id BBDB380626 for ; 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Tue, 15 Mar 2011 21:11:27 +0000 (UTC) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c index 5795c83..52e5e60 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -89,6 +89,7 @@ #define DAVINCI_I2C_MDR_XA BIT(8) #define DAVINCI_I2C_MDR_RM BIT(7) #define DAVINCI_I2C_MDR_IRS BIT(5) +#define DAVINCI_I2C_MDR_FDF BIT(3) #define DAVINCI_I2C_IMR_AAS BIT(6) #define DAVINCI_I2C_IMR_SCD BIT(5) @@ -149,6 +150,36 @@ static void generic_i2c_clock_pulse(unsigned int scl_pin) } } +static void alternate_i2c_clock_pulse(struct davinci_i2c_dev *dev) +{ + u32 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + /* free data format mode */ + flag |= DAVINCI_I2C_MDR_FDF; + /* receive byte */ + flag &= ~DAVINCI_I2C_MDR_TRX; + /* repeat */ + flag |= DAVINCI_I2C_MDR_RM; + + /* + * Write mode register first as needed for correct behaviour + * on OMAP-L138, but don't set STT yet to avoid a race with XRDY + * occuring before we have loaded DXR + */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + + /* Disable receive and transmit interrupts */ + flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); + flag &= ~DAVINCI_I2C_IMR_RRDY; + flag &= ~DAVINCI_I2C_IMR_XRDY; + davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, flag); + + /* Set STT to begin transmit now DXR is loaded */ + flag |= DAVINCI_I2C_MDR_STT; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + + udelay(40*9); +} + /* This routine does i2c bus recovery as specified in the * i2c protocol Rev. 03 section 3.16 titled "Bus clear" */ @@ -163,8 +194,10 @@ static void i2c_recover_bus(struct davinci_i2c_dev *dev) flag |= DAVINCI_I2C_MDR_NACK; /* write the data into mode register */ davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); - if (pdata) + if (pdata->scl_pin) generic_i2c_clock_pulse(pdata->scl_pin); + else + alternate_i2c_clock_pulse(dev); /* Send STOP */ flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); flag |= DAVINCI_I2C_MDR_STP;