From patchwork Thu Jul 7 21:33:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Yariv X-Patchwork-Id: 954402 Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p67LYcV0023271 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 7 Jul 2011 21:34:59 GMT Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p67LXUmq005968 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 7 Jul 2011 16:33:31 -0500 Received: from linux.omap.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep34.itg.ti.com (8.13.7/8.13.8) with ESMTP id p67LXTHY001614; Thu, 7 Jul 2011 16:33:30 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 43EC58062B; Thu, 7 Jul 2011 16:33:29 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id AE7A38062B for ; Thu, 7 Jul 2011 16:33:27 -0500 (CDT) Received: from neches.ext.ti.com (neches.ext.ti.com [192.91.81.29]) by dflp53.itg.ti.com (8.13.8/8.13.8) with ESMTP id p67LXRLk026404 for ; Thu, 7 Jul 2011 16:33:27 -0500 (CDT) Received: from psmtp.com (na3sys009amx195.postini.com [74.125.149.176]) by neches.ext.ti.com (8.13.7/8.13.7) with SMTP id p67LXQna004564 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 7 Jul 2011 16:33:26 -0500 Received: from mail-wy0-f173.google.com ([74.125.82.173]) (using TLSv1) by na3sys009amx195.postini.com ([74.125.148.10]) with SMTP; Thu, 07 Jul 2011 21:33:27 GMT Received: by wyf28 with SMTP id 28so1087674wyf.4 for ; Thu, 07 Jul 2011 14:33:24 -0700 (PDT) Received: by 10.216.55.196 with SMTP id k46mr7069332wec.91.1310074404735; Thu, 07 Jul 2011 14:33:24 -0700 (PDT) Received: from localhost.localdomain (46-116-74-128.bb.netvision.net.il [46.116.74.128]) by mx.google.com with ESMTPS id k57sm134149wed.34.2011.07.07.14.33.22 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jul 2011 14:33:24 -0700 (PDT) From: Ido Yariv To: davinci-linux-open-source@linux.davincidsp.com, linux-arm-kernel@lists.arm.linux.org.uk, linux-mmc@vger.kernel.org Subject: [PATCH 1/5] arm: davinci: Fix low level gpio irq handlers' argument Date: Fri, 8 Jul 2011 00:33:06 +0300 Message-Id: <1310074390-4277-2-git-send-email-ido@wizery.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1310074390-4277-1-git-send-email-ido@wizery.com> References: <1310074390-4277-1-git-send-email-ido@wizery.com> X-pstn-neptune: 0/0/0.00/0 X-pstn-levels: (S:99.90000/99.90000 CV:99.9000 FC:95.5390 LC:95.5390 R:95.9108 P:95.9108 M:97.0282 C:98.6951 ) X-pstn-settings: 2 (0.5000:0.0750) s cv GT3 gt2 gt1 r p m c X-pstn-addresses: from [35/1] Cc: Thomas Gleixner X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 07 Jul 2011 21:34:59 +0000 (UTC) Commit 7416401 ("arm: davinci: Fix fallout from generic irq chip conversion") introduced a bug, causing low level interrupt handlers to get a bogus irq number as an argument. The gpio irq handler falsely assumes that the handler data is the irq base number and that is no longer true. Fix this by converting gpio_irq_handler's bank_irq argument to the corresponding irq base number. Signed-off-by: Ido Yariv CC: Thomas Gleixner --- arch/arm/mach-davinci/gpio.c | 16 ++++++++++++---- 1 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index e722139..db6355a 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -249,8 +249,16 @@ static struct irq_chip gpio_irqchip = { .flags = IRQCHIP_SET_TYPE_MASKED, }; +static unsigned int first_irq_in_bankirq(unsigned int bank_irq) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + /* Each irq bank consists of up to 16 irqs */ + return gpio_to_irq(0) + (16 * (bank_irq - soc_info->gpio_irq)); +} + static void -gpio_irq_handler(unsigned irq, struct irq_desc *desc) +gpio_irq_handler(unsigned bank_irq, struct irq_desc *desc) { struct davinci_gpio_regs __iomem *g; u32 mask = 0xffff; @@ -258,7 +266,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc); /* we only care about one bank */ - if (irq & 1) + if (bank_irq & 1) mask <<= 16; /* temporarily mask (level sensitive) parent IRQ */ @@ -274,11 +282,11 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) if (!status) break; __raw_writel(status, &g->intstat); - if (irq & 1) + if (bank_irq & 1) status >>= 16; /* now demux them to the right lowlevel handler */ - n = (int)irq_get_handler_data(irq); + n = first_irq_in_bankirq(bank_irq); while (status) { res = ffs(status); n += res;