From patchwork Sun Jul 10 13:14:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Yariv X-Patchwork-Id: 961362 Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6ADHHSI031069 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Sun, 10 Jul 2011 13:17:38 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6ADEwXI008655 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 10 Jul 2011 08:14:58 -0500 Received: from linux.omap.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep33.itg.ti.com (8.13.7/8.13.8) with ESMTP id p6ADEvFK003430; Sun, 10 Jul 2011 08:14:58 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 08B048062B; Sun, 10 Jul 2011 08:14:57 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id D56B28062B for ; Sun, 10 Jul 2011 08:14:54 -0500 (CDT) Received: from medina.ext.ti.com (medina.ext.ti.com [192.91.81.31]) by dflp53.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6ADEstc007231 for ; Sun, 10 Jul 2011 08:14:54 -0500 (CDT) Received: from psmtp.com (na3sys009amx201.postini.com [74.125.149.41]) by medina.ext.ti.com (8.13.7/8.13.7) with SMTP id p6ADErAO026187 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Sun, 10 Jul 2011 08:14:54 -0500 Received: from mail-wy0-f173.google.com ([74.125.82.173]) (using TLSv1) by na3sys009amx201.postini.com ([74.125.148.10]) with SMTP; Sun, 10 Jul 2011 06:14:54 PDT Received: by wyf28 with SMTP id 28so2482691wyf.4 for ; Sun, 10 Jul 2011 06:14:52 -0700 (PDT) Received: by 10.216.79.74 with SMTP id h52mr3854105wee.33.1310303691989; Sun, 10 Jul 2011 06:14:51 -0700 (PDT) Received: from localhost.localdomain (46-116-74-128.bb.netvision.net.il [46.116.74.128]) by mx.google.com with ESMTPS id g2sm6388912weg.14.2011.07.10.06.14.49 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 10 Jul 2011 06:14:51 -0700 (PDT) From: Ido Yariv To: davinci-linux-open-source@linux.davincidsp.com, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org Subject: [PATCH v2 1/6] arm: davinci: Fix low level gpio irq handlers' argument Date: Sun, 10 Jul 2011 16:14:34 +0300 Message-Id: <1310303679-17936-2-git-send-email-ido@wizery.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1310303679-17936-1-git-send-email-ido@wizery.com> References: <1310303679-17936-1-git-send-email-ido@wizery.com> X-pstn-neptune: 0/0/0.00/0 X-pstn-levels: (S:99.90000/99.90000 CV:99.9000 FC:95.5390 LC:95.5390 R:95.9108 P:95.9108 M:97.0282 C:98.6951 ) X-pstn-settings: 2 (0.5000:0.0750) s cv GT3 gt2 gt1 r p m c X-pstn-addresses: from [35/1] Cc: Thomas Gleixner X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sun, 10 Jul 2011 13:17:38 +0000 (UTC) Commit 7416401 ("arm: davinci: Fix fallout from generic irq chip conversion") introduced a bug, causing low level interrupt handlers to get a bogus irq number as an argument. The gpio irq handler falsely assumes that the handler data is the irq base number and that is no longer true. Fix this by converting gpio_irq_handler's bank_irq argument to the corresponding irq base number. Signed-off-by: Ido Yariv CC: Thomas Gleixner --- arch/arm/mach-davinci/gpio.c | 32 ++++++++++++++++++++++++++++---- 1 files changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index e722139..ff43e2a 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -249,16 +249,40 @@ static struct irq_chip gpio_irqchip = { .flags = IRQCHIP_SET_TYPE_MASKED, }; +static inline int bankirq_to_irqbase(unsigned int bank_irq) +{ + int gpio; + int index; + + /* Each irq bank consists of up to 16 irqs */ + gpio = 16 * (bank_irq - davinci_soc_info.gpio_irq); + + /* Each controller controls 32 GPIOs */ + index = gpio / 32; + + if (unlikely(!davinci_soc_info.gpio_ctlrs)) + return -EINVAL; + + if (unlikely(index >= davinci_soc_info.gpio_ctlrs_num)) + return -EINVAL; + + return davinci_soc_info.gpio_ctlrs[index].irq_base; +} + static void -gpio_irq_handler(unsigned irq, struct irq_desc *desc) +gpio_irq_handler(unsigned bank_irq, struct irq_desc *desc) { struct davinci_gpio_regs __iomem *g; u32 mask = 0xffff; + int irqbase = bankirq_to_irqbase(bank_irq); + + if (unlikely(irqbase < 0)) + return; g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc); /* we only care about one bank */ - if (irq & 1) + if (bank_irq & 1) mask <<= 16; /* temporarily mask (level sensitive) parent IRQ */ @@ -274,11 +298,11 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) if (!status) break; __raw_writel(status, &g->intstat); - if (irq & 1) + if (bank_irq & 1) status >>= 16; /* now demux them to the right lowlevel handler */ - n = (int)irq_get_handler_data(irq); + n = irqbase; while (status) { res = ffs(status); n += res;