From patchwork Thu Jul 21 09:39:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rajashekhara, Sudhakar" X-Patchwork-Id: 994152 Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6L9s242031315 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 21 Jul 2011 09:54:28 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6L9qqGp005338 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 21 Jul 2011 04:52:52 -0500 Received: from linux.omap.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep33.itg.ti.com (8.13.7/8.13.8) with ESMTP id p6L9qqSE005264; Thu, 21 Jul 2011 04:52:52 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id ED27880627; Thu, 21 Jul 2011 04:52:51 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dbdp20.itg.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by linux.omap.com (Postfix) with ESMTP id B5A4180626 for ; Thu, 21 Jul 2011 04:52:49 -0500 (CDT) Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6L9qlu0000476; Thu, 21 Jul 2011 15:22:47 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Thu, 21 Jul 2011 15:22:46 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with SMTP id p6L9qg60004927; Thu, 21 Jul 2011 15:22:43 +0530 (IST) Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id 0057F158002; Thu, 21 Jul 2011 15:22:41 +0530 (IST) Received: from linux-psp-server.india.ext.ti.com (linux-psp-server [192.168.247.76]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id p6L9qdq28003; Thu, 21 Jul 2011 15:22:40 +0530 (IST) From: "Rajashekhara, Sudhakar" To: Subject: [PATCH] mtd: nand: davinci: Add cpufreq support Date: Thu, 21 Jul 2011 15:09:23 +0530 Message-ID: <1311241163-4576-1-git-send-email-sudhakar.raj@ti.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Cc: davinci-linux-open-source@linux.davincidsp.com, dwmw2@infradead.org X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 21 Jul 2011 09:55:49 +0000 (UTC) This patch adds cpufreq support for NAND driver. During cpufreq transition, 'davinci_aemif_setup_timing()' function will be called to reconfigure that AEMIF timings for the new frequency. Tested on TI DA850/OMAP-L138 EVM. Signed-off-by: Rajashekhara, Sudhakar --- drivers/mtd/nand/davinci_nand.c | 54 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 54 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 1f34951..7e764af 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -74,6 +75,9 @@ struct davinci_nand_info { uint32_t core_chipsel; struct davinci_aemif_timing *timing; +#ifdef CONFIG_CPU_FREQ + struct notifier_block freq_transition; +#endif }; static DEFINE_SPINLOCK(davinci_nand_lock); @@ -519,6 +523,47 @@ static struct nand_ecclayout hwecc4_2048 __initconst = { }, }; +#ifdef CONFIG_CPU_FREQ +static int nand_davinci_cpufreq_transition(struct notifier_block *nb, + unsigned long val, void *data) +{ + struct davinci_nand_info *info; + + info = container_of(nb, struct davinci_nand_info, freq_transition); + + if (val == CPUFREQ_POSTCHANGE) + davinci_aemif_setup_timing(info->timing, info->base, + info->core_chipsel); + + return 0; +} + +static inline int nand_davinci_cpufreq_register(struct davinci_nand_info *info) +{ + info->freq_transition.notifier_call = nand_davinci_cpufreq_transition; + + return cpufreq_register_notifier(&info->freq_transition, + CPUFREQ_TRANSITION_NOTIFIER); +} + +static inline void nand_davinci_cpufreq_deregister(struct davinci_nand_info + *info) +{ + cpufreq_unregister_notifier(&info->freq_transition, + CPUFREQ_TRANSITION_NOTIFIER); +} +#else +static inline int nand_davinci_cpufreq_register(struct davinci_nand_info *info) +{ + return 0; +} + +static inline void nand_davinci_cpufreq_deregister(struct davinci_nand_info + *info) +{ +} +#endif + static int __init nand_davinci_probe(struct platform_device *pdev) { struct davinci_nand_pdata *pdata = pdev->dev.platform_data; @@ -782,12 +827,19 @@ syndrome_done: if (ret < 0) goto err_scan; + ret = nand_davinci_cpufreq_register(info); + if (ret) { + dev_err(&pdev->dev, "failed to register cpufreq\n"); + goto err_cpu_freq_fail; + } + val = davinci_nand_readl(info, NRCSR_OFFSET); dev_info(&pdev->dev, "controller rev. %d.%d\n", (val >> 8) & 0xff, val & 0xff); return 0; +err_cpu_freq_fail: err_scan: err_timing: clk_disable(info->clk); @@ -818,6 +870,8 @@ static int __exit nand_davinci_remove(struct platform_device *pdev) struct davinci_nand_info *info = platform_get_drvdata(pdev); int status; + nand_davinci_cpufreq_deregister(info); + status = mtd_device_unregister(&info->mtd); spin_lock_irq(&davinci_nand_lock);