From patchwork Tue Sep 18 18:35:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 1474261 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by patchwork1.kernel.org (Postfix) with ESMTP id 887E3400EC for ; Tue, 18 Sep 2012 18:38:27 +0000 (UTC) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q8IIb83K001080; Tue, 18 Sep 2012 13:37:08 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8IIb8q1009906; Tue, 18 Sep 2012 13:37:08 -0500 Received: from dlelxv24.itg.ti.com (172.17.1.199) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Tue, 18 Sep 2012 13:37:07 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8IIb8cr012373; Tue, 18 Sep 2012 13:37:08 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id ED89C80628; Tue, 18 Sep 2012 13:37:07 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dlelxv30.itg.ti.com (dlelxv30.itg.ti.com [172.17.2.17]) by linux.omap.com (Postfix) with ESMTP id 7CF5B8062A for ; Tue, 18 Sep 2012 13:35:46 -0500 (CDT) Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8IIZkAh006511; Tue, 18 Sep 2012 13:35:46 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Tue, 18 Sep 2012 13:35:45 -0500 Received: from ares-ubuntu.am.dhcp.ti.com (ares-ubuntu.am.dhcp.ti.com [158.218.103.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8IIZkwS007545; Tue, 18 Sep 2012 13:35:46 -0500 Received: from a0868495 by ares-ubuntu.am.dhcp.ti.com with local (Exim 4.76) (envelope-from ) id 1TE2e9-0001bU-Qs; Tue, 18 Sep 2012 14:35:45 -0400 From: Murali Karicheri To: , , , , , , , Subject: [RFC PATCH 03/10] clk:keystone - add Main PLL clock driver Date: Tue, 18 Sep 2012 14:35:36 -0400 Message-ID: <1347993342-6099-4-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1347993342-6099-1-git-send-email-m-karicheri2@ti.com> References: <1347993342-6099-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com This is the driver for the main PLL clock hardware found on Keystone devices (c6x such as C6678). This driver is implemented as per common clock provider API. The main PLL hardware typically has a multiplier, and a divider. struct clk_keystone_pll_data is used to configure the driver for a specific platform. Signed-off-by: Murali Karicheri diff --git a/drivers/clk/keystone/clk-keystone-pll.c b/drivers/clk/keystone/clk-keystone-pll.c new file mode 100644 index 0000000..0e1a1c4 --- /dev/null +++ b/drivers/clk/keystone/clk-keystone-pll.c @@ -0,0 +1,94 @@ +/* + * Main PLL clk driver for Keystone devices + * + * Copyright (C) 2012 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include + +#include + +/** + * struct clk_pll - DaVinci Main pll clock + * @hw: clk_hw for the pll + * @pll_data: PLL driver specific data + */ +struct clk_pll { + struct clk_hw hw; + struct clk_keystone_pll_data *pll_data; +}; + +#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) + +static unsigned long clk_pllclk_recalc(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pll *pll = to_clk_pll(hw); + struct clk_keystone_pll_data *pll_data = pll->pll_data; + unsigned long rate = parent_rate; + u32 pllm, plld, postdiv, val; + + /* get bit0-5 of PLLM from PLLM PLL control register */ + val = __raw_readl(pll_data->pllm); + pllm = (val & pll_data->pllm_lower_mask); + + /* bit6-12 of PLLM is in Main PLL control register */ + val = __raw_readl(pll_data->main_pll_ctl0); + pllm |= ((val & pll_data->pllm_upper_mask) + >> pll_data->pllm_upper_shift); + plld = (val & pll_data->plld_mask); + postdiv = pll_data->fixed_postdiv; + + rate /= (plld + 1); + rate = (rate * (pllm + 1)); + rate /= postdiv; + + pr_notice("main_pll_clk rate is %ld, postdiv = %d, pllm = %d," \ + "plld = %d\n", rate, postdiv, pllm, plld); + return rate; +} + +static const struct clk_ops clk_pll_ops = { + .recalc_rate = clk_pllclk_recalc, +}; + +struct clk *clk_register_keystone_pll(struct device *dev, const char *name, + const char *parent_name, + struct clk_keystone_pll_data *pll_data) +{ + struct clk_init_data init; + struct clk_pll *pll; + struct clk *clk; + + if (!pll_data) + return ERR_PTR(-ENODEV); + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &clk_pll_ops; + init.flags = 0; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + + pll->pll_data = pll_data; + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} diff --git a/include/linux/platform_data/clk-keystone-pll.h b/include/linux/platform_data/clk-keystone-pll.h new file mode 100644 index 0000000..eecf6a6 --- /dev/null +++ b/include/linux/platform_data/clk-keystone-pll.h @@ -0,0 +1,34 @@ +/* + * TI Keyston clk-pll driver platform data definitions + * + * Copyright (C) 2012 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __CLK_KEYSTONE_PLL_H +#define __CLK_KEYSTONE_PLL_H + +struct clk_keystone_pll_data { + u32 phy_pllm; /* holds lower bits of PLLM */ + u32 phy_main_pll_ctl0; /* holds upper bits of PLLM */ + /* mapped addresses. should be initialized by */ + void __iomem *pllm; + void __iomem *main_pll_ctl0; + u32 pllm_lower_mask; + u32 pllm_upper_mask; + u32 pllm_upper_shift; + u32 plld_mask; + u32 fixed_postdiv; /* use this value for postdiv */ +}; + +extern struct clk *clk_register_keystone_pll(struct device *dev, + const char *name, const char *parent_name, + struct clk_keystone_pll_data *pll_data); +#endif /* CLK_KEYSTONE_PLL_H */