From patchwork Fri Oct 5 13:51:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manjunathappa, Prakash" X-Patchwork-Id: 1553281 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by patchwork2.kernel.org (Postfix) with ESMTP id E7C6CDF24C for ; Fri, 5 Oct 2012 14:09:17 +0000 (UTC) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q95E9HWh017492 for ; Fri, 5 Oct 2012 09:09:17 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q95E9H45008257 for ; Fri, 5 Oct 2012 09:09:17 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Fri, 5 Oct 2012 09:09:17 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id q95E9HK9014992 for ; Fri, 5 Oct 2012 09:09:17 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 526F38063E for ; Fri, 5 Oct 2012 09:09:15 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dbdp20.itg.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by linux.omap.com (Postfix) with ESMTP id 4E07F80626 for ; Fri, 5 Oct 2012 09:09:05 -0500 (CDT) Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q95E94UQ024244; Fri, 5 Oct 2012 19:39:04 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Fri, 5 Oct 2012 19:39:04 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with SMTP id q95E93lT032561; Fri, 5 Oct 2012 19:39:03 +0530 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id E6516158002; Fri, 5 Oct 2012 19:39:03 +0530 (IST) Received: from localhost.localdomain (linux-psp-server [192.168.247.76]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id q95E93726668; Fri, 5 Oct 2012 19:39:03 +0530 (IST) From: "Manjunathappa, Prakash" To: , Subject: [PATCH 2/2] da8xx-fb: cleanup LCDC configurations Date: Fri, 5 Oct 2012 19:21:24 +0530 Message-ID: <1349445084-9857-3-git-send-email-prakash.pm@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1349445084-9857-1-git-send-email-prakash.pm@ti.com> References: <1349445084-9857-1-git-send-email-prakash.pm@ti.com> MIME-Version: 1.0 CC: X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces+patchwork-davinci=patchwork.kernel.org@linux.davincidsp.com Configure below LCDC configurations to optimal values, also have an option configure these optional parameters for platform. 1) AC bias configuration: Required only for passive panels 2) Dma_burst_size: 3) FIFO_DMA_DELAY: 4) FIFO threshold: Does not apply for da830 LCDC. Patch is verified for 16bpp and 24bpp configurations on da830, da850 and am335x EVMs. Signed-off-by: Manjunathappa, Prakash --- arch/arm/mach-davinci/devices-da8xx.c | 27 +++-------------------- drivers/video/da8xx-fb.c | 37 +++++++++++--------------------- include/video/da8xx-fb.h | 22 +------------------ 3 files changed, 18 insertions(+), 68 deletions(-) diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 12a47cd..eb0a1ec 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -524,29 +524,9 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata) } } -static const struct display_panel disp_panel = { - QVGA, - 16, - 16, - COLOR_ACTIVE, -}; - static struct lcd_ctrl_config lcd_cfg = { - &disp_panel, - .ac_bias = 255, - .ac_bias_intrpt = 0, - .dma_burst_sz = 16, + .panel_shade = COLOR_ACTIVE, .bpp = 16, - .fdd = 255, - .tft_alt_mode = 0, - .stn_565_mode = 0, - .mono_8bit_mode = 0, - .invert_line_clock = 1, - .invert_frm_clock = 1, - .sync_edge = 0, - .sync_ctrl = 1, - .raster_order = 0, - .fifo_th = 6, }; struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { @@ -562,7 +542,8 @@ struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = { .lower_margin = 2, .hsync_len = 0, .vsync_len = 0, - .sync = FB_SYNC_CLK_INVERT, + .sync = FB_SYNC_CLK_INVERT | + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .flag = 0, }, }; @@ -580,7 +561,7 @@ struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = { .lower_margin = 2, .hsync_len = 41, .vsync_len = 10, - .sync = 0, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .flag = 0, }, }; diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index bacf82b..36af88b 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -339,10 +339,9 @@ static int lcd_cfg_dma(int burst_size, int fifo_th) reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); break; case 16: + default: /* Configuring for highest burst */ reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); break; - default: - return -EINVAL; } reg |= (fifo_th << 8); @@ -387,7 +386,8 @@ static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, lcdc_write(reg, LCD_RASTER_TIMING_1_REG); } -static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) +static int lcd_cfg_display(const struct lcd_ctrl_config *cfg, + struct fb_videomode *panel) { u32 reg; u32 reg_int; @@ -396,7 +396,7 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) LCD_MONO_8BIT_MODE | LCD_MONOCHROME_MODE); - switch (cfg->p_disp_panel->panel_shade) { + switch (cfg->panel_shade) { case MONOCHROME: reg |= LCD_MONOCHROME_MODE; if (cfg->mono_8bit_mode) @@ -409,7 +409,9 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) break; case COLOR_PASSIVE: - if (cfg->stn_565_mode) + /* AC bias applicable only for Pasive panels */ + lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); + if (cfg->bpp == 12 && cfg->stn_565_mode) reg |= LCD_STN_565_ENABLE; break; @@ -430,22 +432,19 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) reg = lcdc_read(LCD_RASTER_TIMING_2_REG); - if (cfg->sync_ctrl) - reg |= LCD_SYNC_CTRL; - else - reg &= ~LCD_SYNC_CTRL; + reg |= LCD_SYNC_CTRL; if (cfg->sync_edge) reg |= LCD_SYNC_EDGE; else reg &= ~LCD_SYNC_EDGE; - if (cfg->invert_line_clock) + if (panel->sync & FB_SYNC_HOR_HIGH_ACT) reg |= LCD_INVERT_LINE_CLOCK; else reg &= ~LCD_INVERT_LINE_CLOCK; - if (cfg->invert_frm_clock) + if (panel->sync & FB_SYNC_VERT_HIGH_ACT) reg |= LCD_INVERT_FRAME_CLOCK; else reg &= ~LCD_INVERT_FRAME_CLOCK; @@ -690,9 +689,6 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, if (ret < 0) return ret; - /* Configure the AC bias properties. */ - lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); - /* Configure the vertical and horizontal sync properties. */ lcd_cfg_vertical_sync(panel->lower_margin, panel->vsync_len, panel->upper_margin); @@ -700,18 +696,12 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, panel->left_margin); /* Configure for disply */ - ret = lcd_cfg_display(cfg); + ret = lcd_cfg_display(cfg, panel); if (ret < 0) return ret; - if (QVGA != cfg->p_disp_panel->panel_type) - return -EINVAL; + bpp = cfg->bpp; - if (cfg->bpp <= cfg->p_disp_panel->max_bpp && - cfg->bpp >= cfg->p_disp_panel->min_bpp) - bpp = cfg->bpp; - else - bpp = cfg->p_disp_panel->max_bpp; if (bpp == 12) bpp = 16; ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres, @@ -1323,8 +1313,7 @@ static int __devinit fb_probe(struct platform_device *device) da8xx_fb_var.yres = lcd_panel_info->yres; da8xx_fb_var.yres_virtual = lcd_panel_info->yres * LCD_NUM_BUFFERS; - da8xx_fb_var.grayscale = - lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; + da8xx_fb_var.grayscale = lcd_cfg->panel_shade == MONOCHROME ? 1 : 0; da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; da8xx_fb_var.hsync_len = lcd_panel_info->hsync_len; diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h index a6796ff..3eada34 100644 --- a/include/video/da8xx-fb.h +++ b/include/video/da8xx-fb.h @@ -14,10 +14,6 @@ #include -enum panel_type { - QVGA = 0 -}; - enum panel_shade { MONOCHROME = 0, COLOR_ACTIVE, @@ -29,13 +25,6 @@ enum raster_load_mode { LOAD_PALETTE, }; -struct display_panel { - enum panel_type panel_type; /* QVGA */ - int max_bpp; - int min_bpp; - enum panel_shade panel_shade; -}; - struct da8xx_lcdc_platform_data { void *controller_data; void (*panel_power_ctrl)(int); @@ -43,7 +32,7 @@ struct da8xx_lcdc_platform_data { }; struct lcd_ctrl_config { - const struct display_panel *p_disp_panel; + enum panel_shade panel_shade; /* AC Bias Pin Frequency */ int ac_bias; @@ -69,18 +58,9 @@ struct lcd_ctrl_config { /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ unsigned char mono_8bit_mode; - /* Invert line clock */ - unsigned char invert_line_clock; - - /* Invert frame clock */ - unsigned char invert_frm_clock; - /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ unsigned char sync_edge; - /* Horizontal and Vertical Sync: Control: 0=ignore */ - unsigned char sync_ctrl; - /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ unsigned char raster_order;