From patchwork Fri Jan 11 00:23:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tivy, Robert" X-Patchwork-Id: 1963351 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by patchwork1.kernel.org (Postfix) with ESMTP id 13D1D3FF0F for ; Fri, 11 Jan 2013 00:30:44 +0000 (UTC) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r0B0Qp8i008133; Thu, 10 Jan 2013 18:26:51 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0B0QpHb004420; Thu, 10 Jan 2013 18:26:51 -0600 Received: from dlelxv23.itg.ti.com (172.17.1.198) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Thu, 10 Jan 2013 18:26:51 -0600 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0B0Qpl9011190; Thu, 10 Jan 2013 18:26:51 -0600 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 0612280626; Thu, 10 Jan 2013 18:26:51 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dlelxv30.itg.ti.com (dlelxv30.itg.ti.com [172.17.2.17]) by linux.omap.com (Postfix) with ESMTP id 3075F8062F for ; Thu, 10 Jan 2013 18:25:02 -0600 (CST) Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0B0P1JO032719; Thu, 10 Jan 2013 18:25:02 -0600 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Thu, 10 Jan 2013 18:25:02 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0B0P1UN008548; Thu, 10 Jan 2013 18:25:01 -0600 Received: from sanblnx02.sanb.design.ti.com (sanblnx02.sanb.design.ti.com [146.252.160.81]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r0B0P0w25222; Thu, 10 Jan 2013 18:25:00 -0600 (CST) Received: from sanblnx02.sanb.design.ti.com (localhost [127.0.0.1]) by sanblnx02.sanb.design.ti.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id r0B0OwpZ000871; Thu, 10 Jan 2013 16:24:58 -0800 Received: (from a0783933@localhost) by sanblnx02.sanb.design.ti.com (8.13.6/8.13.6/Submit) id r0B0OwXf000868; Thu, 10 Jan 2013 16:24:58 -0800 From: Robert Tivy To: , , , , , , , Subject: [PATCH v5 5/9] ARM: davinci: New reset functionality/API provided for Davinci DSP Date: Thu, 10 Jan 2013 16:23:23 -0800 Message-ID: <1357863807-380-6-git-send-email-rtivy@ti.com> X-Mailer: git-send-email 1.7.9.4 In-Reply-To: <1357863807-380-1-git-send-email-rtivy@ti.com> References: <1357863807-380-1-git-send-email-rtivy@ti.com> MIME-Version: 1.0 X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com Since there is no general "reset" support for SoC devices, and since the remoteproc driver needs explicit control of the DSP's reset line, a new Davinci-specific API is added. This private API will disappear with DT migration. Some discussion regarding a proposed DT "reset" binding is here: https://patchwork.kernel.org/patch/1635051/ Modified davinci_clk_init() to set clk "reset" function for clocks that indicate PSC_LRST support. Also fixed indentation issue with function opening curly brace. Signed-off-by: Robert Tivy --- arch/arm/mach-davinci/clock.c | 39 +++++++++++++++++++++++++++- arch/arm/mach-davinci/clock.h | 3 +++ arch/arm/mach-davinci/include/mach/clock.h | 3 +++ arch/arm/mach-davinci/include/mach/psc.h | 3 +++ arch/arm/mach-davinci/psc.c | 25 ++++++++++++++++++ 5 files changed, 72 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 34668ea..e1dd522 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -52,6 +52,40 @@ static void __clk_disable(struct clk *clk) __clk_disable(clk->parent); } +int davinci_clk_reset(struct clk *clk, bool reset) +{ + unsigned long flags; + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + spin_lock_irqsave(&clockfw_lock, flags); + if (clk->flags & CLK_PSC) + davinci_psc_reset_config(clk->gpsc, clk->lpsc, reset); + spin_unlock_irqrestore(&clockfw_lock, flags); + + return 0; +} +EXPORT_SYMBOL(davinci_clk_reset); + +int davinci_clk_reset_assert(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk) || !clk->reset) + return -EINVAL; + + return clk->reset(clk, true); +} +EXPORT_SYMBOL(davinci_clk_reset_assert); + +int davinci_clk_reset_deassert(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk) || !clk->reset) + return -EINVAL; + + return clk->reset(clk, false); +} +EXPORT_SYMBOL(davinci_clk_reset_deassert); + int clk_enable(struct clk *clk) { unsigned long flags; @@ -535,7 +569,7 @@ int davinci_set_refclk_rate(unsigned long rate) } int __init davinci_clk_init(struct clk_lookup *clocks) - { +{ struct clk_lookup *c; struct clk *clk; size_t num_clocks = 0; @@ -576,6 +610,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks) if (clk->lpsc) clk->flags |= CLK_PSC; + if (clk->flags & PSC_LRST) + clk->reset = davinci_clk_reset; + clk_register(clk); num_clocks++; diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 46f0f1b..8694b39 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -103,6 +103,7 @@ struct clk { unsigned long (*recalc) (struct clk *); int (*set_rate) (struct clk *clk, unsigned long rate); int (*round_rate) (struct clk *clk, unsigned long rate); + int (*reset) (struct clk *clk, bool reset); }; /* Clock flags: SoC-specific flags start at BIT(16) */ @@ -112,6 +113,7 @@ struct clk { #define PRE_PLL BIT(4) /* source is before PLL mult/div */ #define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */ #define PSC_FORCE BIT(6) /* Force module state transtition */ +#define PSC_LRST BIT(8) /* Use local reset on enable/disable */ #define CLK(dev, con, ck) \ { \ @@ -126,6 +128,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); int davinci_set_refclk_rate(unsigned long rate); int davinci_simple_set_rate(struct clk *clk, unsigned long rate); +int davinci_clk_reset(struct clk *clk, bool reset); extern struct platform_device davinci_wdt_device; extern void davinci_watchdog_reset(struct platform_device *); diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h index a3b0402..3e8af6a 100644 --- a/arch/arm/mach-davinci/include/mach/clock.h +++ b/arch/arm/mach-davinci/include/mach/clock.h @@ -18,4 +18,7 @@ struct clk; extern int clk_register(struct clk *clk); extern void clk_unregister(struct clk *clk); +int davinci_clk_reset_assert(struct clk *c); +int davinci_clk_reset_deassert(struct clk *c); + #endif diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 40a0027..0580133 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -246,6 +246,7 @@ #define MDSTAT_STATE_MASK 0x3f #define PDSTAT_STATE_MASK 0x1f +#define MDCTL_LRST BIT(8) #define MDCTL_FORCE BIT(31) #define PDCTL_NEXT BIT(0) #define PDCTL_EPCGOOD BIT(8) @@ -253,6 +254,8 @@ #ifndef __ASSEMBLER__ extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); +extern void davinci_psc_reset_config(unsigned int ctlr, unsigned int id, + bool reset); extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, bool enable, u32 flags); diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index bddaba9..b6f0c10 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -48,6 +48,31 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) return mdstat & BIT(12); } +/* Control "reset" line associated with PSC domain */ +void davinci_psc_reset_config(unsigned int ctlr, unsigned int id, bool reset) +{ + u32 mdctl; + void __iomem *psc_base; + struct davinci_soc_info *soc_info = &davinci_soc_info; + + if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { + pr_warn("PSC: Bad psc data: 0x%x[%d]\n", + (int)soc_info->psc_bases, ctlr); + return; + } + + psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); + + mdctl = readl(psc_base + MDCTL + 4 * id); + if (reset) + mdctl &= ~MDCTL_LRST; + else + mdctl |= MDCTL_LRST; + writel(mdctl, psc_base + MDCTL + 4 * id); + + iounmap(psc_base); +} + /* Enable or disable a PSC domain */ void davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, bool enable, u32 flags)