From patchwork Sat Nov 2 15:39:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 3130821 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 63E579F43F for ; Sat, 2 Nov 2013 15:41:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2AEBA20258 for ; Sat, 2 Nov 2013 15:41:39 +0000 (UTC) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB1E4201B7 for ; Sat, 2 Nov 2013 15:41:37 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id rA2FfbRt008406 for ; Sat, 2 Nov 2013 10:41:37 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id rA2Ffaf6018465 for ; Sat, 2 Nov 2013 10:41:37 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Sat, 2 Nov 2013 10:41:36 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id rA2FfaBM029115 for ; Sat, 2 Nov 2013 10:41:36 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 8D69980635 for ; Sat, 2 Nov 2013 09:41:36 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp52.itg.ti.com (dflp52.itg.ti.com [128.247.22.96]) by linux.omap.com (Postfix) with ESMTP id DF1638062C for ; Sat, 2 Nov 2013 09:40:48 -0600 (CST) Received: from white.ext.ti.com (white.ext.ti.com [192.94.93.38]) by dflp52.itg.ti.com (8.13.7/8.13.8) with ESMTP id rA2FeNpr014838 for ; Sat, 2 Nov 2013 10:40:43 -0500 (CDT) Received: from mail6.bemta8.messagelabs.com (mail6.bemta8.messagelabs.com [216.82.243.55]) by white.ext.ti.com (8.13.7/8.13.7) with ESMTP id rA2FeNdu029915 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Sat, 2 Nov 2013 10:40:23 -0500 Received: from [216.82.242.147:1201] by server-8.bemta-8.messagelabs.com id 32/F0-19102-6EC15725; Sat, 02 Nov 2013 15:40:22 +0000 X-Env-Sender: prabhakar.csengg@gmail.com X-Msg-Ref: server-5.tower-95.messagelabs.com!1383406820!20952138!1 X-Originating-IP: [209.85.220.54] X-SpamReason: No, hits=0.0 required=7.0 tests=ML_RADAR_SPEW_LINKS_14, SUBJECT_RANDOMQ,spamassassin: X-StarScan-Received: X-StarScan-Version: 6.9.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 30646 invoked from network); 2 Nov 2013 15:40:21 -0000 Received: from mail-pa0-f54.google.com (HELO mail-pa0-f54.google.com) (209.85.220.54) by server-5.tower-95.messagelabs.com with RC4-SHA encrypted SMTP; 2 Nov 2013 15:40:21 -0000 Received: by mail-pa0-f54.google.com with SMTP id fa1so5305615pad.13 for ; Sat, 02 Nov 2013 08:40:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lulWpwUq0wZpthQFhNEl2lkb4dPU5xs9/gQOWK4oU8E=; b=RfMzqfaHa90o6lmXE1tEGOuqktxPX6KkOUsO5goo9uTUzUbcxP0BziLpmf2s+C7c8+ qO3whkCqMSbHrTB4CZnre8SJF2XjB6zFc/+tywUGIqYAWl5w/fJYr4MMfxmcq5rBLc8p HSo6Yf5sHGSjFyWXsp5MiXiz+FGHIFAZXqOt2DgRJW/t5ZVHHskR2h19AOwHl3ttUnI/ KRqEt/6coGg5Nv1lvi8Mu84jqqtbBQDzSCvu+CZqrg2j8mAPRnOm+mReevwo/pQwjdSA yMgw+iNDWbWxmiBAEVfVE/ZhQOyGHp8YHbXXGMQLpDrmgEhwns80zMC8MKU69cMPbsTU s/cw== X-Received: by 10.66.132.69 with SMTP id os5mr8490502pab.114.1383406819943; Sat, 02 Nov 2013 08:40:19 -0700 (PDT) Received: from localhost.localdomain ([49.200.27.40]) by mx.google.com with ESMTPSA id qp10sm20456849pab.13.2013.11.02.08.40.10 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 02 Nov 2013 08:40:18 -0700 (PDT) From: "Lad, Prabhakar" To: Sekhar Nori , Linus Walleij , Subject: [PATCH v4 3/6] gpio: davinci: use irqdomain Date: Sat, 2 Nov 2013 21:09:32 +0530 Message-ID: <1383406775-14902-4-git-send-email-prabhakar.csenng@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1383406775-14902-1-git-send-email-prabhakar.csenng@gmail.com> References: <1383406775-14902-1-git-send-email-prabhakar.csenng@gmail.com> CC: Mark Rutland , Alex Elder , , Russell King , Pawel Moll , Ian Campbell , Stephen Warren , , , Rob Herring , , Rob Landley , Grant Likely , X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: Errors-To: davinci-linux-open-source-bounces+patchwork-davinci=patchwork.kernel.org@linux.davincidsp.com X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Lad, Prabhakar" This patch converts the davinci gpio driver to use irqdomain support. Signed-off-by: Lad, Prabhakar --- arch/arm/mach-davinci/da830.c | 1 - arch/arm/mach-davinci/da850.c | 1 - arch/arm/mach-davinci/dm355.c | 1 - arch/arm/mach-davinci/dm365.c | 1 - arch/arm/mach-davinci/dm644x.c | 1 - arch/arm/mach-davinci/dm646x.c | 1 - drivers/gpio/gpio-davinci.c | 49 ++++++++++++++++++---------- include/linux/platform_data/gpio-davinci.h | 3 +- 8 files changed, 32 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index 0813b51..fb72035 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -1153,7 +1153,6 @@ static struct davinci_id da830_ids[] = { static struct davinci_gpio_platform_data da830_gpio_platform_data = { .ngpio = 128, - .intc_irq_num = DA830_N_CP_INTC_IRQ, }; int __init da830_register_gpio(void) diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 352984e..4379317 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1283,7 +1283,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config static struct davinci_gpio_platform_data da850_gpio_platform_data = { .ngpio = 144, - .intc_irq_num = DA850_N_CP_INTC_IRQ, }; int __init da850_register_gpio(void) diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index ef9ff1f..5160aed 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -900,7 +900,6 @@ static struct resource dm355_gpio_resources[] = { static struct davinci_gpio_platform_data dm355_gpio_platform_data = { .ngpio = 104, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, }; int __init dm355_gpio_register(void) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 1511a06..4fe29fa 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -713,7 +713,6 @@ static struct resource dm365_gpio_resources[] = { static struct davinci_gpio_platform_data dm365_gpio_platform_data = { .ngpio = 104, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, .gpio_unbanked = 8, }; diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 143a321..178cb68 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -786,7 +786,6 @@ static struct resource dm644_gpio_resources[] = { static struct davinci_gpio_platform_data dm644_gpio_platform_data = { .ngpio = 71, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, }; int __init dm644x_gpio_register(void) diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 2a73f29..01c576f 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -763,7 +763,6 @@ static struct resource dm646x_gpio_resources[] = { static struct davinci_gpio_platform_data dm646x_gpio_platform_data = { .ngpio = 43, - .intc_irq_num = DAVINCI_N_AINTC_IRQ, }; int __init dm646x_gpio_register(void) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 95c6df1..bcb6d8d 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -292,7 +293,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) __raw_writel(status, &g->intstat); /* now demux them to the right lowlevel handler */ - n = d->irq_base; + n = irq_find_mapping(d->irq_domain, 0); if (irq & 1) { n += 16; status >>= 16; @@ -313,10 +314,7 @@ static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) { struct davinci_gpio_controller *d = chip2controller(chip); - if (d->irq_base >= 0) - return d->irq_base + offset; - else - return -ENODEV; + return irq_find_mapping(d->irq_domain, offset); } static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) @@ -373,6 +371,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); struct davinci_gpio_platform_data *pdata = dev->platform_data; struct davinci_gpio_regs __iomem *g; + int gpio_irq = 0; ngpio = pdata->ngpio; res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); @@ -402,9 +401,15 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) */ for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { chips[bank].chip.to_irq = gpio_to_irq_banked; - chips[bank].irq_base = pdata->gpio_unbanked - ? -EINVAL - : (pdata->intc_irq_num + gpio); + if (!pdata->gpio_unbanked) { + chips[bank].irq_domain = + irq_domain_add_linear(NULL, 32, + &irq_domain_simple_ops, + NULL); + + if (!chips[bank].irq_domain) + return -ENOMEM; + } } /* @@ -445,9 +450,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we * then chain through our own handler. */ - for (gpio = 0, irq = gpio_to_irq(0), bank = 0; - gpio < ngpio; - bank++, bank_irq++) { + for (gpio = 0, irq = 0, bank = 0; gpio < ngpio; bank++, bank_irq++) { unsigned i; /* disabled by default, enabled only as needed */ @@ -465,12 +468,22 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) */ irq_set_handler_data(bank_irq, &chips[gpio / 32]); - for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { - irq_set_chip(irq, &gpio_irqchip); - irq_set_chip_data(irq, (__force void *)g); - irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); - irq_set_handler(irq, handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); + if (!(bank % 2)) + irq = 0; + else + irq = 16; + + for (i = 0; i < 16 && gpio < ngpio; i++, gpio++) { + int irqno = + irq_create_mapping(chips[gpio / 32].irq_domain, + i + irq); + + irq_set_chip(irqno, &gpio_irqchip); + irq_set_chip_data(irqno, (__force void *)g); + irq_set_handler_data(irqno, (void *)__gpio_mask(gpio)); + irq_set_handler(irqno, handle_simple_irq); + set_irq_flags(irqno, IRQF_VALID); + gpio_irq++; } binten |= BIT(bank); @@ -483,7 +496,7 @@ done: */ __raw_writel(binten, gpio_base + BINTEN); - printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); + pr_info("DaVinci: %d gpio irqs\n", gpio_irq); return 0; } diff --git a/include/linux/platform_data/gpio-davinci.h b/include/linux/platform_data/gpio-davinci.h index 6efd202..fbe2f75 100644 --- a/include/linux/platform_data/gpio-davinci.h +++ b/include/linux/platform_data/gpio-davinci.h @@ -28,13 +28,12 @@ enum davinci_gpio_type { struct davinci_gpio_platform_data { u32 ngpio; u32 gpio_unbanked; - u32 intc_irq_num; }; struct davinci_gpio_controller { struct gpio_chip chip; - int irq_base; + struct irq_domain *irq_domain; /* Serialize access to GPIO registers */ spinlock_t lock; void __iomem *regs;