From patchwork Thu Nov 21 18:15:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 3220191 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8D931C045B for ; Thu, 21 Nov 2013 18:18:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0BCD32074B for ; Thu, 21 Nov 2013 18:18:30 +0000 (UTC) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6D65F206CE for ; Thu, 21 Nov 2013 18:18:28 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id rALIHNKt001645; Thu, 21 Nov 2013 12:17:23 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id rALIHKem012662; Thu, 21 Nov 2013 12:17:23 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Thu, 21 Nov 2013 12:17:21 -0600 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id rALIHJqm023749; Thu, 21 Nov 2013 12:17:20 -0600 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 6A57A8062B; Thu, 21 Nov 2013 12:17:19 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflxv17.itg.ti.com (dflxv17.itg.ti.com [128.247.5.93]) by linux.omap.com (Postfix) with ESMTP id 3044480627 for ; Thu, 21 Nov 2013 12:16:06 -0600 (CST) Received: from neches.ext.ti.com (neches.ext.ti.com [192.91.81.29]) by dflxv17.itg.ti.com (8.14.3/8.13.8) with ESMTP id rALIG6BM014312 for ; Thu, 21 Nov 2013 12:16:06 -0600 Received: from mail6.bemta8.messagelabs.com (mail6.bemta8.messagelabs.com [216.82.243.55]) by neches.ext.ti.com (8.13.7/8.13.7) with ESMTP id rALIG5Vw011847 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 21 Nov 2013 12:16:05 -0600 Received: from [216.82.241.195:2993] by server-3.bemta-8.messagelabs.com id 08/20-06553-5ED4E825; Thu, 21 Nov 2013 18:16:05 +0000 X-Env-Sender: prabhakar.csengg@gmail.com X-Msg-Ref: server-8.tower-119.messagelabs.com!1385057763!22792731!1 X-Originating-IP: [209.85.220.50] X-SpamReason: No, hits=0.0 required=7.0 tests=ML_RADAR_SPEW_LINKS_14, SUBJECT_RANDOMQ,spamassassin: X-StarScan-Received: X-StarScan-Version: 6.9.13; banners=-,-,- X-VirusChecked: Checked Received: (qmail 1408 invoked from network); 21 Nov 2013 18:16:04 -0000 Received: from mail-pa0-f50.google.com (HELO mail-pa0-f50.google.com) (209.85.220.50) by server-8.tower-119.messagelabs.com with RC4-SHA encrypted SMTP; 21 Nov 2013 18:16:04 -0000 Received: by mail-pa0-f50.google.com with SMTP id kl14so103441pab.23 for ; Thu, 21 Nov 2013 10:16:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kictxiWvO8RbPD+J1CMLKjmNpQf05qntYt4yCXKfQxo=; b=mL0aA7F9RgZ2fzeEH+qi4BOy/B54D6G0c1Lujz5XkA8DZgbG/0CE6eEc9bWms0rd6E Gjehla48HJX85s6g4rJEBHHYgOZyE11fXsYf/FgEzSs0qSorNC1v4332wZLYXTKDIUB9 wyOgNbWjFYvuVm3PE9zuGOVdVLJ9VPIlIYmcNIU3G09oGV3FTlui4q7twrvqKxC/191s kGntJdUZgOClYaZXG9I3E2zO2Vo0KaEdIA+sZqkNCCr+tIhiofoDAVFgLMZna1EMo8Lw PA9Tsrp1fpeTRV2qBdmhEdwwh5i53TO5V9C7hfVkOJIkLibj79vTEH9ZU4Y1mRjqJbXl AMsw== X-Received: by 10.68.59.202 with SMTP id b10mr7835391pbr.78.1385057763170; Thu, 21 Nov 2013 10:16:03 -0800 (PST) Received: from localhost.localdomain ([59.161.53.225]) by mx.google.com with ESMTPSA id bl8sm43648678pad.17.2013.11.21.10.15.54 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 21 Nov 2013 10:16:01 -0800 (PST) From: Prabhakar Lad To: Sekhar Nori , Linus Walleij , Grygorii Strashko Subject: [PATCH v6 2/6] This patch converts the davinci gpio driver to use irqdomain support. Date: Thu, 21 Nov 2013 23:45:27 +0530 Message-ID: <1385057731-4348-3-git-send-email-prabhakar.csengg@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1385057731-4348-1-git-send-email-prabhakar.csengg@gmail.com> References: <1385057731-4348-1-git-send-email-prabhakar.csengg@gmail.com> CC: Mark Rutland , , DLOS , Pawel Moll , , Stephen Warren , LKML , Rob Herring , , Rob Landley , Grant Likely , Ian Campbell , LAK X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Lad, Prabhakar" Signed-off-by: Lad, Prabhakar [grygorii.strashko@ti.com: - switch to use one irq-domain per all GPIO banks - keep irq_create_mapping() call in gpio_to_irq_banked() as it simply transformed to irq_find_mapping() if IRQ mapping exist already] Signed-off-by: Grygorii Strashko Acked-by: Linus Walleij --- drivers/gpio/gpio-davinci.c | 80 ++++++++++++++++------------ include/linux/platform_data/gpio-davinci.h | 2 +- 2 files changed, 48 insertions(+), 34 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 1f33fcd..4d6adbc 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -282,8 +283,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) desc->irq_data.chip->irq_ack(&desc->irq_data); while (1) { u32 status; - int n; - int res; + int bit; /* ack any irqs */ status = readl(&g->intstat) & mask; @@ -292,17 +292,13 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) writel(status, &g->intstat); /* now demux them to the right lowlevel handler */ - n = d->irq_base; - if (irq & 1) { - n += 16; - status >>= 16; - } while (status) { - res = ffs(status); - n += res; - generic_handle_irq(n - 1); - status >>= res; + bit = __ffs(status); + status &= ~BIT(bit); + generic_handle_irq( + irq_find_mapping(d->irq_domain, + d->chip.base + bit)); } } desc->irq_data.chip->irq_unmask(&desc->irq_data); @@ -313,10 +309,7 @@ static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) { struct davinci_gpio_controller *d = chip2controller(chip); - if (d->irq_base >= 0) - return d->irq_base + offset; - else - return -ENODEV; + return irq_create_mapping(d->irq_domain, d->chip.base + offset); } static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) @@ -354,6 +347,27 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) return 0; } +static int +davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) +{ + struct davinci_gpio_regs __iomem *g = gpio2regs(hw); + + irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, + "davinci_gpio"); + irq_set_irq_type(irq, IRQ_TYPE_NONE); + irq_set_chip_data(irq, (__force void *)g); + irq_set_handler_data(irq, (void *)__gpio_mask(hw)); + set_irq_flags(irq, IRQF_VALID); + + return 0; +} + +static const struct irq_domain_ops davinci_gpio_irq_ops = { + .map = davinci_gpio_irq_map, + .xlate = irq_domain_xlate_onetwocell, +}; + /* * NOTE: for suspend/resume, probably best to make a platform_device with * suspend_late/resume_resume calls hooking into results of the set_wake() @@ -373,6 +387,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); struct davinci_gpio_platform_data *pdata = dev->platform_data; struct davinci_gpio_regs __iomem *g; + struct irq_domain *irq_domain; ngpio = pdata->ngpio; res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); @@ -396,6 +411,20 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) } clk_prepare_enable(clk); + irq = irq_alloc_descs(-1, 0, ngpio, 0); + if (irq < 0) { + dev_err(dev, "Couldn't allocate IRQ numbers\n"); + return -ENODEV; + } + + irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0, + &davinci_gpio_irq_ops, + chips); + if (!irq_domain) { + dev_err(dev, "Couldn't register an IRQ domain\n"); + return -ENODEV; + } + /* * Arrange gpio_to_irq() support, handling either direct IRQs or * banked IRQs. Having GPIOs in the first GPIO bank use direct @@ -404,9 +433,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) */ for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { chips[bank].chip.to_irq = gpio_to_irq_banked; - chips[bank].irq_base = pdata->gpio_unbanked - ? -EINVAL - : (pdata->intc_irq_num + gpio); + if (!pdata->gpio_unbanked) + chips[bank].irq_domain = irq_domain; } /* @@ -449,11 +477,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we * then chain through our own handler. */ - for (gpio = 0, irq = gpio_to_irq(0), bank = 0; - gpio < ngpio; - bank++, bank_irq++) { - unsigned i; - + for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { /* disabled by default, enabled only as needed */ g = gpio2regs(gpio); writel(~0, &g->clr_falling); @@ -469,14 +493,6 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) */ irq_set_handler_data(bank_irq, &chips[gpio / 32]); - for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { - irq_set_chip(irq, &gpio_irqchip); - irq_set_chip_data(irq, (__force void *)g); - irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); - irq_set_handler(irq, handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); - } - binten |= BIT(bank); } @@ -487,8 +503,6 @@ done: */ writel(binten, gpio_base + BINTEN); - printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); - return 0; } diff --git a/include/linux/platform_data/gpio-davinci.h b/include/linux/platform_data/gpio-davinci.h index 6efd202..0c3551b 100644 --- a/include/linux/platform_data/gpio-davinci.h +++ b/include/linux/platform_data/gpio-davinci.h @@ -34,7 +34,7 @@ struct davinci_gpio_platform_data { struct davinci_gpio_controller { struct gpio_chip chip; - int irq_base; + struct irq_domain *irq_domain; /* Serialize access to GPIO registers */ spinlock_t lock; void __iomem *regs;