From patchwork Thu Mar 13 09:18:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 3823231 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5139BBF540 for ; Thu, 13 Mar 2014 09:21:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 71D8A201BB for ; Thu, 13 Mar 2014 09:21:22 +0000 (UTC) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 90135201FD for ; Thu, 13 Mar 2014 09:21:21 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s2D9LKWQ006822 for ; Thu, 13 Mar 2014 04:21:20 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2D9LK62013774 for ; Thu, 13 Mar 2014 04:21:20 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Thu, 13 Mar 2014 04:21:20 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2D9LKs9023311 for ; Thu, 13 Mar 2014 04:21:20 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 48AA580626 for ; Thu, 13 Mar 2014 03:21:20 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dlelxv90.itg.ti.com (dlelxv90.itg.ti.com [172.17.2.17]) by linux.omap.com (Postfix) with ESMTP id CB6E880627 for ; Thu, 13 Mar 2014 03:19:12 -0600 (CST) Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2D9JC9U031479; Thu, 13 Mar 2014 04:19:12 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Thu, 13 Mar 2014 04:19:12 -0500 Received: from dflp32.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s2D9Ifhc005531; Thu, 13 Mar 2014 04:19:09 -0500 From: Peter Ujfalusi To: , , , , Subject: [PATCH 07/18] DMA: edma: Use different eventq for cyclic channels Date: Thu, 13 Mar 2014 11:18:29 +0200 Message-ID: <1394702320-21743-8-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1394702320-21743-1-git-send-email-peter.ujfalusi@ti.com> References: <1394702320-21743-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 CC: , , Liam Girdwood , Jyri Sarha , Tony Lindgren , Mark Brown , , , X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces+patchwork-davinci=patchwork.kernel.org@linux.davincidsp.com X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To improve latency with cyclic DMA operation it is preferred to use different eventq/tc than the default which is used by all other drivers (mmc, spi, i2c, etc). When preparing the cyclic dma ask for non default queue for the channel which is going to be used with cyclic mode. Signed-off-by: Peter Ujfalusi --- drivers/dma/edma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 86d6a3fb0d92..604c7c94c731 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -624,6 +624,9 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( edesc->pset[i].opt |= TCINTEN; } + /* Use different eventq/tc for cyclic DMA to reduce latency */ + edma_request_non_default_queue(echan->ch_num); + return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); }