From patchwork Tue Apr 1 13:06:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 3922671 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1908B9F388 for ; Tue, 1 Apr 2014 13:11:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 572D120221 for ; Tue, 1 Apr 2014 13:11:35 +0000 (UTC) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 613DE20380 for ; Tue, 1 Apr 2014 13:11:34 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s31DAn9E031608; Tue, 1 Apr 2014 08:10:49 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s31DAnK0014673; Tue, 1 Apr 2014 08:10:49 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Tue, 1 Apr 2014 08:10:49 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s31DAn0C013206; Tue, 1 Apr 2014 08:10:49 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 577FC8062A; Tue, 1 Apr 2014 07:10:49 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dlelxv90.itg.ti.com (dlelxv90.itg.ti.com [172.17.2.17]) by linux.omap.com (Postfix) with ESMTP id 1BF218062A for ; Tue, 1 Apr 2014 07:06:43 -0600 (CST) Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s31D6h30010186; Tue, 1 Apr 2014 08:06:43 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Tue, 1 Apr 2014 08:06:42 -0500 Received: from dflp33.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s31D6Hfi012538; Tue, 1 Apr 2014 08:06:40 -0500 From: Peter Ujfalusi To: , , Subject: [PATCH v2 08/14] DMA: edma: Use different eventq for cyclic channels Date: Tue, 1 Apr 2014 16:06:09 +0300 Message-ID: <1396357575-30585-9-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1396357575-30585-1-git-send-email-peter.ujfalusi@ti.com> References: <1396357575-30585-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 CC: , , , , , , X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To improve latency with cyclic DMA operation it is preferred to use different eventq/tc than the default which is used by all other drivers (mmc, spi, i2c, etc). When preparing the cyclic dma ask for non default queue for the channel which is going to be used with cyclic mode. Signed-off-by: Peter Ujfalusi --- drivers/dma/edma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 1dd9e8806975..10048b40fac8 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -628,6 +628,9 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( edesc->pset[i].opt |= TCINTEN; } + /* Use different eventq/tc for cyclic DMA to reduce latency */ + edma_request_non_default_queue(echan->ch_num); + return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); }