From patchwork Tue Jul 8 10:46:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 4503781 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A60BFBEEAA for ; Tue, 8 Jul 2014 10:47:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C8A7220320 for ; Tue, 8 Jul 2014 10:47:06 +0000 (UTC) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0FD1020270 for ; Tue, 8 Jul 2014 10:47:05 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s68Al49E026594 for ; Tue, 8 Jul 2014 05:47:04 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s68Al3qX019086 for ; Tue, 8 Jul 2014 05:47:04 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Tue, 8 Jul 2014 05:47:03 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s68Al3S6018742 for ; Tue, 8 Jul 2014 05:47:03 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 47EC680628 for ; Tue, 8 Jul 2014 05:47:03 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflxv15.itg.ti.com (dflxv15.itg.ti.com [128.247.5.124]) by linux.omap.com (Postfix) with ESMTP id 4CFA180628 for ; Tue, 8 Jul 2014 05:46:54 -0500 (CDT) Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s68Akq4e018497; Tue, 8 Jul 2014 05:46:54 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Tue, 8 Jul 2014 05:46:51 -0500 Received: from szilva.Elisa (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s68AkdtZ024976; Tue, 8 Jul 2014 05:46:49 -0500 From: Peter Ujfalusi To: , , Subject: [PATCH 3/3] dma: edma: Serve cyclic (audio) channels with high priority queue Date: Tue, 8 Jul 2014 13:46:38 +0300 Message-ID: <1404816398-12338-4-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1404816398-12338-1-git-send-email-peter.ujfalusi@ti.com> References: <1404816398-12338-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 CC: , , , , , X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces+patchwork-davinci=patchwork.kernel.org@linux.davincidsp.com X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move the DMA channel used in cyclic mode (audio) to the highest priority event queue which helps to reduce audio problems. When the channel is terminated, move it back to the default queue. Signed-off-by: Peter Ujfalusi --- drivers/dma/edma.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index b512caf46944..fe55f78ea137 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -256,8 +256,13 @@ static int edma_terminate_all(struct edma_chan *echan) * echan->edesc is NULL and exit.) */ if (echan->edesc) { + int cyclic = echan->edesc->cyclic; echan->edesc = NULL; edma_stop(echan->ch_num); + /* Move the cyclic channel back to default queue */ + if (cyclic) + edma_assign_channel_eventq(echan->ch_num, + EVENTQ_DEFAULT); } vchan_get_all_descriptors(&echan->vchan, &head); @@ -724,6 +729,9 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( edesc->pset[i].param.opt |= TCINTEN; } + /* Place the cyclic channel to highest priority queue */ + edma_assign_channel_eventq(echan->ch_num, EVENTQ_0); + return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); }