From patchwork Thu Sep 24 18:38:54 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 49960 Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n8OIbw6X028941 for ; Thu, 24 Sep 2009 18:37:58 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id n8OIaULm023217 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 24 Sep 2009 13:36:31 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id n8OIaSwD011548; Thu, 24 Sep 2009 13:36:28 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 1AE1480627; Thu, 24 Sep 2009 13:36:28 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id 0624280626 for ; Thu, 24 Sep 2009 13:36:27 -0500 (CDT) Received: from white.ext.ti.com (localhost [127.0.0.1]) by dflp53.itg.ti.com (8.13.8/8.13.8) with ESMTP id n8OIaQbq021007 for ; Thu, 24 Sep 2009 13:36:26 -0500 (CDT) Received: from mail5-va3-R.bigfish.com (mail-va3.bigfish.com [216.32.180.111]) by white.ext.ti.com (8.13.7/8.13.7) with ESMTP id n8OIaPe0015429 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL) for ; Thu, 24 Sep 2009 13:36:26 -0500 Received: from mail5-va3 (localhost.localdomain [127.0.0.1]) by mail5-va3-R.bigfish.com (Postfix) with ESMTP id CC0F1FC025F for ; Thu, 24 Sep 2009 18:36:25 +0000 (UTC) X-SpamScore: 10 X-BigFish: vps10(zcb8kzzz1202hzzz2dh6bh259o66h) X-Spam-TCS-SCL: 5:0 X-FB-SS: 5, X-MS-Exchange-Organization-Antispam-Report: OrigIP: 63.81.120.155; Service: EHS Received: by mail5-va3 (MessageSwitch) id 1253817381629734_11205; Thu, 24 Sep 2009 18:36:21 +0000 (UCT) Received: from imap.sh.mvista.com (unknown [63.81.120.155]) by mail5-va3.bigfish.com (Postfix) with ESMTP id 71BFAA4804F for ; Thu, 24 Sep 2009 18:36:21 +0000 (UTC) Received: from wasted.dev.rtsoft.ru (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 0B7E53EC9; Thu, 24 Sep 2009 11:36:20 -0700 (PDT) From: Sergei Shtylyov Organization: MontaVista Software Inc. To: khilman@deeprootsystems.com Date: Thu, 24 Sep 2009 22:38:54 +0400 User-Agent: KMail/1.5 MIME-Version: 1.0 Content-Disposition: inline Message-Id: <200909242238.54334.sshtylyov@ru.mvista.com> Cc: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH 2/3] DA8xx: CPPI 4.1 platfrom code (take 3) X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.4 Precedence: list List-Id: davinci-linux-open-source.linux.davincidsp.com List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com Add the function to initialize the CPPI 4.1 subsystem along with the data describing CPPI 4.1 queue manager and DMA block found in DA8xx chips. Signed-off-by: Sergei Shtylyov --- The patch is against the recent DaVinci tree. Changes since the previous take: - fixed the prototype of the empty implementation of da8xx_cppi41_init(). Argh... :-/ arch/arm/mach-davinci/devices-da8xx.c | 112 +++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/da8xx.h | 2 2 files changed, 114 insertions(+) Index: linux-davinci/arch/arm/mach-davinci/devices-da8xx.c =================================================================== --- linux-davinci.orig/arch/arm/mach-davinci/devices-da8xx.c +++ linux-davinci/arch/arm/mach-davinci/devices-da8xx.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "clock.h" @@ -488,3 +489,114 @@ int da8xx_register_rtc(void) return platform_device_register(&da8xx_rtc_device); } + +#ifdef CONFIG_CPPI41 + +static const struct cppi41_tx_ch tx_ch_info[] = { + [0] = { + .port_num = 1, + .num_tx_queue = 2, + .tx_queue = { { 0, 16 }, { 0, 17 } } + }, + [1] = { + .port_num = 2, + .num_tx_queue = 2, + .tx_queue = { { 0, 18 }, { 0, 19 } } + }, + [2] = { + .port_num = 3, + .num_tx_queue = 2, + .tx_queue = { { 0, 20 }, { 0, 21 } } + }, + [3] = { + .port_num = 4, + .num_tx_queue = 2, + .tx_queue = { { 0, 22 }, { 0, 23 } } + } +}; + +/* DMA block configuration */ +const struct cppi41_dma_block cppi41_dma_block[1] = { + [0] = { + .global_ctrl_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x1000), + .ch_ctrl_stat_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x1800), + .sched_ctrl_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x2000), + .sched_table_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x2800), + .num_tx_ch = 4, + .num_rx_ch = 4, + .tx_ch_info = tx_ch_info + } +}; +EXPORT_SYMBOL(cppi41_dma_block); + +/* Queues 0 to 27 are pre-assigned, others are spare */ +static const u32 assigned_queues[] = { 0x0fffffff, 0 }; + +/* Queue manager information */ +const struct cppi41_queue_mgr cppi41_queue_mgr[1] = { + [0] = { + .q_mgr_rgn_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x4000), + .desc_mem_rgn_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x5000), + .q_mgmt_rgn_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x6000), + .q_stat_rgn_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x6800), + + .num_queue = 64, + .queue_types = CPPI41_FREE_DESC_BUF_QUEUE | + CPPI41_UNASSIGNED_QUEUE, + .base_fdbq_num = 0, + .assigned = assigned_queues + } +}; + +const u8 cppi41_num_queue_mgr = 1; +const u8 cppi41_num_dma_block = 1; + +/* Fair DMA scheduling */ +static const u8 dma_sched_table[] = { + 0x00, 0x80, 0x01, 0x81, 0x02, 0x82, 0x03, 0x83 +}; + +int __init da8xx_cppi41_init(void) +{ + struct clk *usb20_clk; + int ret; + + /* CPPI 4.1 is clocked by USB 2.0 clock. */ + usb20_clk = clk_get(NULL, "usb20"); + if (IS_ERR(usb20_clk)) { + ret = PTR_ERR(usb20_clk); + pr_warning("%s: clk_get() call failed: %d\n", __func__, ret); + return ret; + } + clk_enable(usb20_clk); + + /* We provide no memory for the queue manager's linking RAM region 0. */ + ret = cppi41_queue_mgr_init(0, 0, 0); + if (ret) { + pr_warning("%s: queue manager initialization failed: %d\n", + __func__, ret); + return ret; + } + + /* Allocate 32 (2^5) DMA teardown descriptors from queue manager 0. */ + ret = cppi41_dma_ctrlr_init(0, 0, 5); + if (ret) { + pr_warning("%s: DMA controller initialization failed: %d\n", + __func__, ret); + return ret; + } + + ret = cppi41_dma_sched_init(0, dma_sched_table, + sizeof(dma_sched_table)); + if (ret) + pr_warning("%s: DMA scheduler initialization failed: %d\n", + __func__, ret); + return ret; +} + +#else +int __init da8xx_cppi41_init(void) +{ + return 0; +} +#endif /* CONFIG_CPPI41 */ Index: linux-davinci/arch/arm/mach-davinci/include/mach/da8xx.h =================================================================== --- linux-davinci.orig/arch/arm/mach-davinci/include/mach/da8xx.h +++ linux-davinci/arch/arm/mach-davinci/include/mach/da8xx.h @@ -74,6 +74,8 @@ extern void __iomem *da8xx_syscfg_base; void __init da830_init(void); void __init da850_init(void); +int da8xx_cppi41_init(void); + int da8xx_register_edma(void); int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); int da8xx_register_watchdog(void);