From patchwork Thu Oct 4 15:48:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: davide.bonfanti@bticino.it X-Patchwork-Id: 1546971 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by patchwork1.kernel.org (Postfix) with ESMTP id BE0B53FC1A for ; Thu, 4 Oct 2012 15:51:26 +0000 (UTC) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q94FnGNQ003677; Thu, 4 Oct 2012 10:49:16 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q94FnGNY012754; Thu, 4 Oct 2012 10:49:16 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Thu, 4 Oct 2012 10:49:16 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id q94FnGSi009600; Thu, 4 Oct 2012 10:49:16 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 5DFB880627; Thu, 4 Oct 2012 10:49:16 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp51.itg.ti.com (dflp51.itg.ti.com [128.247.22.94]) by linux.omap.com (Postfix) with ESMTP id E0F4280626 for ; Thu, 4 Oct 2012 10:49:14 -0500 (CDT) Received: from neches.ext.ti.com (neches.ext.ti.com [192.91.81.29]) by dflp51.itg.ti.com (8.13.7/8.13.8) with ESMTP id q94FnEQr013493 for ; Thu, 4 Oct 2012 10:49:14 -0500 (CDT) Received: from psmtp.com (na3sys009amx201.postini.com [74.125.149.41]) by neches.ext.ti.com (8.13.7/8.13.7) with SMTP id q94FnCMS000483 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 4 Oct 2012 10:49:13 -0500 Received: from bticino.it ([91.208.195.90]) (using TLSv1) by na3sys009amx201.postini.com ([74.125.148.10]) with SMTP; Thu, 04 Oct 2012 15:49:13 GMT Received: from ([10.31.15.91]) by smtp1.bticino.it with ESMTP id 5RSHRF1.81962322; Thu, 04 Oct 2012 17:49:02 +0200 Received: from localhost ([10.39.10.63]) by notes-mta.srvnts.grpleg.com (Lotus Domino Release 8.5.3FP1) with ESMTP id 2012100417485751-399 ; Thu, 4 Oct 2012 17:48:57 +0200 Date: Thu, 4 Oct 2012 17:48:06 +0200 From: Davide Bonfanti To: Linux DaVinci Kernel List Subject: [PATCH v1] DaVinci: dm365: added sdram dma clock divide ratio management Message-ID: <20121004154748.GA19445@btlists.it> MIME-Version: 1.0 X-attached: none User-Agent: Mutt/1.5.20 (2009-06-14) X-MIMETrack: Itemize by SMTP Server on NOTES-MTA/BTICINO/IT(Release 8.5.3FP1|March 07, 2012) at 04/10/2012 17:48:57, Serialize by Router on IT-VAR-HUB-01/SRV/GRPLEG(Release 8.5.3FP1|March 07, 2012) at 04/10/2012 17.49.02, Serialize complete at 04/10/2012 17.49.02 Content-Disposition: inline X-pstn-levels: (S:72.10399/99.90000 CV:99.9000 FC:95.5390 LC:95.5390 R:95.9108 P:95.9108 M:97.0282 C:98.6951 ) X-pstn-dkim: 0 skipped:not-enabled X-pstn-settings: 2 (0.5000:0.5000) s cv gt3 gt2 gt1 r p m c X-pstn-addresses: from [82/3] CC: X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com This patch applies to: v2.6.32.17-6450-g6725c92 commit 74f19831af149656f705b3b8a8c32bdf8c1c74fb The CLKDIV register is then used to select a divide ratio of the SDRAM(DMA) clock for the pixel clock frequency which is used to clock the data into the PCLK. The CLKDIV register is then used to select a divide ratio of the SDRAM(DMA) clock for the pixel clock frequency which is used to clock the data into the PCLK. The value of this register depends on the resize ratios of the IPIPE resizers and the available SDRAM system bandwidth. Once defined input and output resolutions to the Resizer, the clock must be at least MAX(input_resolution, output_resolution) * framerate. This is a rough approximation, the resizer needs some additional lines and pixels at the frames edges so a slightly higher clock than above is needed. A 12.5% of increment is implemented. If resizer clock is too high, then what will happen is that resizer will try to read pixels at every clock cycle. If there is someone else running in the system (VPSS capture or ARM or codec) then if the resizer will fail to read the pixel at any given moment due to other master using the DDR at that time, IT WILL ABORT the operation causing an incomplete frame in memory. Signed-off-by: Davide Bonfanti Signed-off-by: Angelo Aresi --- drivers/char/dm365_ipipe.c | 48 ++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 48 insertions(+), 0 deletions(-) diff --git a/drivers/char/dm365_ipipe.c b/drivers/char/dm365_ipipe.c index a945122..6161875 100644 --- a/drivers/char/dm365_ipipe.c +++ b/drivers/char/dm365_ipipe.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include @@ -599,6 +601,43 @@ static void calculate_resize_ratios(struct ipipe_params *param, int index) (param->rsz_rsc_param[index].o_vsz + 1); } +/* calculate_sdram_dma_divide_ratio() + * calculate the divide ratio of the SDRAM(DMA). This is called after setting + * the input/output size since the speed depends on video size and framrate + */ +static void calculate_sdram_dma_divide_ratio(struct ipipe_params *param, + struct v4l2_fract fps) +{ + struct clk *vpss_clk; + unsigned long vpss_rate, pixels = 0; + + vpss_clk = clk_get(NULL, "vpss_master"); + vpss_rate = clk_get_rate(vpss_clk); + clk_put(vpss_clk); + + pixels = (param->ipipe_hsz + 1) * (param->ipipe_vsz + 1); + if (param->rsz_en[RSZ_A]) { + if (pixels < (param->rsz_rsc_param[RSZ_A].o_hsz + 1) * + (param->rsz_rsc_param[RSZ_A].o_vsz + 1)) + pixels = (param->rsz_rsc_param[RSZ_A].o_hsz + 1) * + (param->rsz_rsc_param[RSZ_A].o_vsz + 1); + } + if (param->rsz_en[RSZ_B]) { + if (pixels < (param->rsz_rsc_param[RSZ_B].o_hsz + 1) * + (param->rsz_rsc_param[RSZ_B].o_vsz + 1)) + pixels = (param->rsz_rsc_param[RSZ_B].o_hsz + 1) * + (param->rsz_rsc_param[RSZ_B].o_vsz + 1); + } + param->ipipeif_param.var.if_5_1.clk_div.m = 1; /*numerator*/ + /* apply a 12.5% of margin for front/back porch */ + pixels += pixels >> 3; + + param->ipipeif_param.var.if_5_1.clk_div.n = vpss_rate / + (pixels * fps.denominator / fps.numerator); + param->ipipeif_param.clock_select = SDRAM_CLK; + +} + static int ipipe_do_hw_setup(struct device *dev, void *config) { struct ipipe_params *param = (struct ipipe_params *)config; @@ -615,6 +654,9 @@ static int ipipe_do_hw_setup(struct device *dev, void *config) calculate_resize_ratios(param, RSZ_A); if (param->rsz_en[RSZ_B]) calculate_resize_ratios(param, RSZ_B); + calculate_sdram_dma_divide_ratio(param, + ((struct vpfe_device *) + dev_get_drvdata(dev))->std_info.fps); ret = ipipe_hw_setup(param); } mutex_unlock(&oper_state.lock); @@ -3132,6 +3174,9 @@ static int configure_resizer_in_ss_mode(struct device *dev, (param->rsz_rsc_param[RSZ_B].o_vsz + 1); } } + calculate_sdram_dma_divide_ratio(param, + ((struct vpfe_device *) + dev_get_drvdata(dev))->std_info.fps); } mutex_unlock(&oper_state.lock); return 0; @@ -3597,6 +3642,9 @@ static int configure_previewer_in_ss_mode(struct device *dev, calculate_resize_ratios(param, RSZ_B); calculate_sdram_offsets(param, RSZ_B); } + calculate_sdram_dma_divide_ratio(param, + ((struct vpfe_device *) + dev_get_drvdata(dev))->std_info.fps); } else { struct rsz_output_spec *output_specs = kmalloc(sizeof(struct rsz_output_spec),