From patchwork Wed Jan 9 12:47:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 1952581 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by patchwork2.kernel.org (Postfix) with ESMTP id 0D3D8DF25A for ; Wed, 9 Jan 2013 12:52:00 +0000 (UTC) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r09Cm4lj026215; Wed, 9 Jan 2013 06:48:04 -0600 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r09Cm4Yu002795; Wed, 9 Jan 2013 06:48:04 -0600 Received: from dlelxv24.itg.ti.com (172.17.1.199) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Wed, 9 Jan 2013 06:48:04 -0600 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id r09Cm4Vp026683; Wed, 9 Jan 2013 06:48:04 -0600 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 20E6E80627; Wed, 9 Jan 2013 06:48:04 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dbdp20.itg.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by linux.omap.com (Postfix) with ESMTP id E092280626 for ; Wed, 9 Jan 2013 06:47:55 -0600 (CST) Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r09ClpS0022129; Wed, 9 Jan 2013 18:17:52 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Wed, 9 Jan 2013 18:17:51 +0530 Received: from [172.24.132.233] (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id r09ClkI4032112; Wed, 9 Jan 2013 18:17:46 +0530 Message-ID: <50ED66F2.8050006@ti.com> Date: Wed, 9 Jan 2013 18:17:46 +0530 From: Sekhar Nori User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: "Kumar, Anil" Subject: Re: [PATCH V2 3/3] ARM: davinci: da850: add NAND driver entries References: <1357633220-29827-1-git-send-email-anilkumar.v@ti.com> <1357633220-29827-4-git-send-email-anilkumar.v@ti.com> In-Reply-To: <1357633220-29827-4-git-send-email-anilkumar.v@ti.com> CC: , , , , X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com On 1/8/2013 1:50 PM, Kumar, Anil wrote: > Add NAND driver entries to export NAND functionality on da850 EVM and > NAND pinctrl node to do pin mux according to pinctrl-single driver. Subject line should have DT and da850 evm somewhere. Otherwise NAND has been supported on DA850 for long. > > Signed-off-by: Kumar, Anil > --- > :100644 100644 c7609d0... 382a7da... M arch/arm/boot/dts/da850-evm.dts > :100644 100644 e9c6e82... 16e2ac2... M arch/arm/boot/dts/da850.dtsi > arch/arm/boot/dts/da850-evm.dts | 19 +++++++++++++++++++ > arch/arm/boot/dts/da850.dtsi | 13 +++++++++++++ > 2 files changed, 32 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts > index c7609d0..382a7da 100644 > --- a/arch/arm/boot/dts/da850-evm.dts > +++ b/arch/arm/boot/dts/da850-evm.dts > @@ -28,4 +28,23 @@ > status = "okay"; > }; > }; > + nand_cs3@62000000 { > + status = "okay"; > + }; > +}; > +&pmx_core{ > + pinctrl-names = "default"; > + pinctrl-0 = < > + &nand_cs3_pins > + >; This means that the NAND pins are configured even if NAND is not probed. Right? This can be moved into the nand_cs3 node to avoid that. And then when used with Linus Walleij's patch "drivers/pinctrl: grab default handles from device core" which should be accepted soon, the pins will be automatically setup when the NAND gets probed. > + > + nand_cs3_pins: pinmux_nand_pins { > + pinctrl-single,bits = < > + 0x1c 0x00110000 0x00ff0000 /* EMA_OE, EMA_WE */ > + 0x1c 0x00000110 0x00000ff0 /* EMA_CS[4],EMA_CS[3]*/ > + 0x24 0x11111111 0xffffffff /* EMA_D[0], EMA_D[1], EMA_D[2], EMA_D[3], > + EMA_D[4], EMA_D[5], EMA_D[6], EMA_D[7] */ > + 0x30 0x01100000 0x0ff00000 /* EMA_A[1], EMA_A[2] */ > + >; > + }; I suspect a number of other boards using NAND on CS3 would have to repeat these configurations. It will be better to move them into the da850.dtsi file so it can be reused. Since I am new to the DT and pinctrl stuff, I had to actually try these to make sure what I am suggesting isn't nonsense. I came up with this patch on top of your series. Please test it at your end and also see if you are happy with the changes. Thanks, Sekhar ---8<---- diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 382a7da..52abb9d 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -30,21 +30,8 @@ }; nand_cs3@62000000 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_cs3_pins>; }; }; -&pmx_core{ - pinctrl-names = "default"; - pinctrl-0 = < - &nand_cs3_pins - >; - nand_cs3_pins: pinmux_nand_pins { - pinctrl-single,bits = < - 0x1c 0x00110000 0x00ff0000 /* EMA_OE, EMA_WE */ - 0x1c 0x00000110 0x00000ff0 /* EMA_CS[4],EMA_CS[3]*/ - 0x24 0x11111111 0xffffffff /* EMA_D[0], EMA_D[1], EMA_D[2], EMA_D[3], - EMA_D[4], EMA_D[5], EMA_D[6], EMA_D[7] */ - 0x30 0x01100000 0x0ff00000 /* EMA_A[1], EMA_A[2] */ - >; - }; -}; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 6ab9730..c4b21a8 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -38,7 +38,25 @@ pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; status = "disabled"; + + nand_cs3_pins: pinmux_nand_pins { + pinctrl-single,bits = < + /* EMA_OE, EMA_WE */ + 0x1c 0x00110000 0x00ff0000 + /* EMA_CS[4],EMA_CS[3]*/ + 0x1c 0x00000110 0x00000ff0 + /* + * EMA_D[0], EMA_D[1], EMA_D[2], + * EMA_D[3], EMA_D[4], EMA_D[5], + * EMA_D[6], EMA_D[7] + */ + 0x24 0x11111111 0xffffffff + /* EMA_A[1], EMA_A[2] */ + 0x30 0x01100000 0x0ff00000 + >; + }; }; + serial0: serial@1c42000 { compatible = "ns16550a"; reg = <0x42000 0x100>;