From patchwork Mon Jun 7 10:15:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raffaele Recalcati X-Patchwork-Id: 104679 Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o57AITMv009171 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Mon, 7 Jun 2010 10:19:09 GMT Received: from dlep35.itg.ti.com ([157.170.170.118]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o57AFPbU017755 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 7 Jun 2010 05:15:25 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o57AFOYO006058; Mon, 7 Jun 2010 05:15:25 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id B313D80627; Mon, 7 Jun 2010 05:15:24 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp51.itg.ti.com (dflp51.itg.ti.com [128.247.22.94]) by linux.omap.com (Postfix) with ESMTP id 8C3DA80626 for ; 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c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=mQjDMePNCEKqXhyMdpORJgcxBNgD3Rc/EulqrN37mO5DjmIJpmge9y2cfMQVi8eUry kfa/LnaR3QUuc6wPUthCCV5jVvfz9Pt6Gzm80V1sz1ShW+Y9jMMhGBuZIopSOSRalC9a VXrELVP+yLg2mOJ1gZL0xM2l653yqdNOri30E= MIME-Version: 1.0 Received: by 10.231.139.148 with SMTP id e20mr4273646ibu.164.1275905720902; Mon, 07 Jun 2010 03:15:20 -0700 (PDT) Received: by 10.231.172.16 with HTTP; Mon, 7 Jun 2010 03:15:20 -0700 (PDT) Date: Mon, 7 Jun 2010 12:15:20 +0200 Message-ID: Subject: [PATCH 02/12] spi: davinci: Added support for chip select using gpio From: Raffaele Recalcati To: davinci-linux-open-source X-pstn-neptune: 0/0/0.00/0 X-pstn-levels: (S:49.09028/99.90000 CV:99.9000 FC:95.5390 LC:95.5390 R:95.9108 P:95.9108 M:97.0282 C:98.6951 ) X-pstn-settings: 2 (0.5000:0.5000) s cv gt3 gt2 gt1 r p m c X-pstn-addresses: from [db-null] X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 07 Jun 2010 10:19:10 +0000 (UTC) diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index a146849..42fd4a4 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -677,10 +677,12 @@ void __init dm365_init_spi0(unsigned chipselect_mask, davinci_cfg_reg(DM365_SPI0_SDO); /* not all slaves will be wired up */ - if (chipselect_mask & BIT(0)) - davinci_cfg_reg(DM365_SPI0_SDENA0); - if (chipselect_mask & BIT(1)) - davinci_cfg_reg(DM365_SPI0_SDENA1); + if (!((unsigned long) info->controller_data)) { + if (chipselect_mask & BIT(0)) + davinci_cfg_reg(DM365_SPI0_SDENA0); + if (chipselect_mask & BIT(1)) + davinci_cfg_reg(DM365_SPI0_SDENA1); + } spi_register_board_info(info, len); diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 95afb6b..6a305ca 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -29,6 +29,7 @@ #include #include +#include #include #include @@ -270,18 +271,25 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) pdata = davinci_spi->pdata; /* - * Board specific chip select logic decides the polarity and cs - * line for the controller - */ + * Board specific chip select logic decides the polarity and cs + * line for the controller + */ if (value == BITBANG_CS_INACTIVE) { - set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); - - data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; - iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); + if ((unsigned long) spi->controller_data) { + gpio_set_value(spi->controller_data, !(spi->mode & SPI_CS_HIGH)); + } else { + set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT); + data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT; + iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); + } while ((ioread32(davinci_spi->base + SPIBUF) - & SPIBUF_RXEMPTY_MASK) == 0) + & SPIBUF_RXEMPTY_MASK) == 0) cpu_relax(); + } else { + if ((unsigned long) spi->controller_data) { + gpio_set_value(spi->controller_data, (spi->mode & SPI_CS_HIGH)); + }