From patchwork Tue Jul 29 14:19:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Cormier X-Patchwork-Id: 4640611 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D89D2C0338 for ; Tue, 29 Jul 2014 14:21:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 68BAD2010C for ; Tue, 29 Jul 2014 14:21:08 +0000 (UTC) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 01127200F0 for ; Tue, 29 Jul 2014 14:21:06 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6TEK6ah000624; Tue, 29 Jul 2014 09:20:06 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6TEK52Z019792; Tue, 29 Jul 2014 09:20:05 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Tue, 29 Jul 2014 09:20:05 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6TEK4EX009952; Tue, 29 Jul 2014 09:20:04 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 15AF580627; Tue, 29 Jul 2014 09:20:04 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dlelxv84.itg.ti.com (dlelxv84.itg.ti.com [172.17.0.246]) by linux.omap.com (Postfix) with ESMTP id 8AC2F80626 for ; Tue, 29 Jul 2014 09:20:02 -0500 (CDT) Received: from red.ext.ti.com (red.ext.ti.com [192.94.93.37]) by dlelxv84.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6TEK2lI023450 for ; Tue, 29 Jul 2014 09:20:02 -0500 Received: from mail6.bemta7.messagelabs.com (mail6.bemta7.messagelabs.com [216.82.255.55]) by red.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6TEJxic001256 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 29 Jul 2014 09:20:02 -0500 Received: from [216.82.253.67:55646] by server-4.bemta-7.messagelabs.com id 08/F8-28388-F8DA7D35; Tue, 29 Jul 2014 14:19:59 +0000 X-Env-Sender: jcormier@criticallink.com X-Msg-Ref: server-7.tower-158.messagelabs.com!1406643597!18821215!1 X-Originating-IP: [209.85.220.174] X-SpamReason: No, hits=1.7 required=7.0 tests=BODY_RANDOM_LONG, HTML_10_20,HTML_MESSAGE,RCVD_BY_IP X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8080 invoked from network); 29 Jul 2014 14:19:57 -0000 Received: from mail-vc0-f174.google.com (HELO mail-vc0-f174.google.com) (209.85.220.174) by server-7.tower-158.messagelabs.com with RC4-SHA encrypted SMTP; 29 Jul 2014 14:19:57 -0000 Received: by mail-vc0-f174.google.com with SMTP id la4so13635650vcb.33 for ; Tue, 29 Jul 2014 07:19:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc :content-type; bh=bh9uZSTgVBGmfcSDDsKpNcqwl8Xr43VVIpdow4YVpNA=; b=Cfai2c5YT6UNL5oRbqZKks8367+fFA/szSp3HlpshsjidP7i1aJ33tUn0NeUA+UMjO 0z8Q9GLsa71QUZuEtr4nD3gBU9t6aHO6IdfZAdqQYt+N2B7nryzBR4vTJtHMX2QiK1Xw rc7yPO0rWI1TZRU9zgj+/0/O3VGum9UwTUQu7qUumt7vQUpn8o/Tf5zaVIBhFaqz8+XI E84G8MZVUcXnfN5DudzxXbRbeuuMH71LHjHu+AttBF+iCfY7y0Jpjnuk98E0ifrP47gi 4xW4t82Y9f9YiPzSg9F+v8iZbTqW8cRD/LeldhY7Y2vnJapR6smXQTqR+pIUWITd37w+ L6gg== X-Gm-Message-State: ALoCoQmrd3BMJvWgGk4uF2jELN8NsOoCp534HM3wA1mZnjrqb/jrUhedZCh7HoD3GhJw2WNJ6vaD X-Received: by 10.220.1.5 with SMTP id 5mr1171161vcd.74.1406643596658; Tue, 29 Jul 2014 07:19:56 -0700 (PDT) MIME-Version: 1.0 Received: by 10.220.192.136 with HTTP; Tue, 29 Jul 2014 07:19:36 -0700 (PDT) From: Jon Cormier Date: Tue, 29 Jul 2014 10:19:36 -0400 Message-ID: Subject: i2c-davinci.c: CPU FREQ causes lock up due to xfr_complete To: CC: Tim Iskander X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00,HTML_MESSAGE, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reported issue: 1. Enable I2C1, flash the new kernel and reboot 2. Immediately after reboot, attempt to change the processor clock: "echo 456000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed" 3. Process blocks However, if we do the following: 1. Enable I2C1, flash the new kernel and reboot 2. Immediately after reboot, run: "i2cdetect -y 2 0x08 0x08" or just "i2cdetect -y 2" 3. Then run: "echo 456000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed" 4. Command succeeds Here's the kernel hung task stack trace: INFO: task sh:1428 blocked for more than 120 seconds. "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. sh D c026dc74 0 1428 1426 0x00000000 [] (schedule+0x2a8/0x334) from [] (schedule_timeout+0x1c/0x218) [] (schedule_timeout+0x1c/0x218) from [] (wait_for_common+0xf0/0x1b8) [] (wait_for_common+0xf0/0x1b8) from [] (i2c_davinci_cpufreq_transition+0x18/0x50) [] (i2c_davinci_cpufreq_transition+0x18/0x50) from [] (notifier_call_chain+0x38/0x68) [] (notifier_call_chain+0x38/0x68) from [] (__srcu_notifier_call_chain+0x40/0x58) [] (__srcu_notifier_call_chain+0x40/0x58) from [] (srcu_notifier_call_chain+0x14/0x18) [] (srcu_notifier_call_chain+0x14/0x18) from [] (cpufreq_notify_transition+0xc8/0xfc) [] (cpufreq_notify_transition+0xc8/0xfc) from [] (davinci_target+0x144/0x154) [] (davinci_target+0x144/0x154) from [] (__cpufreq_driver_target+0x28/0x38) [] (__cpufreq_driver_target+0x28/0x38) from [] (cpufreq_set+0x54/0x70) [] (cpufreq_set+0x54/0x70) from [] (store_scaling_setspeed+0x58/0x6c) [] (store_scaling_setspeed+0x58/0x6c) from [] (store+0x58/0x74) [] (store+0x58/0x74) from [] (sysfs_write_file+0x108/0x140) [] (sysfs_write_file+0x108/0x140) from [] (vfs_write+0xb0/0x118) [] (vfs_write+0xb0/0x118) from [] (sys_write+0x3c/0x68) [] (sys_write+0x3c/0x68) from [] (ret_fast_syscall+0x0/0x28) Kernel panic - not syncing: hung_task: blocked tasks [] (unwind_backtrace+0x0/0xd0) from [] (panic+0x44/0xc8) [] (panic+0x44/0xc8) from [] (watchdog+0x1d4/0x21c) [] (watchdog+0x1d4/0x21c) from [] (kthread+0x78/0x80) [] (kthread+0x78/0x80) from [] (kernel_thread_exit+0x0/0x8) According to the stack trace the kernel gets stuck in the "i2c_davinci_cpufreq_transition" function when it calls "wait_for_completion(&dev->xfr_complete);" The two other places this xfr_complete variable is referenced is the init_completion in the probe and the complete at the end of the i2c_davinci_xfer function. My understanding as to what this was intended for was to ensure that a transfer in progress completed before changing the clock frequency. But as its currently done the only thing it does is make sure there has been a completed i2c transfer on this device ever. Is my understanding correct? Currently the workaround is to simply disable the wait_for_completion as seen below. How would you fix this to ensure a transfer in progress completes before changing clocks without hanging if no transfer was ever attempted? i2c_davinci_calc_clk_dividers(dev); Patch were this was introduced: sha: 82c0de11b734c5acec13c0f6007466da81cd16d9 i2c:davinci:Add cpufreq support diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c index a76d85f..564247f 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -596,7 +596,7 @@ static int i2c_davinci_cpufreq_transition(struct notifier_block *nb, dev = container_of(nb, struct davinci_i2c_dev, freq_transition); if (val == CPUFREQ_PRECHANGE) { - wait_for_completion(&dev->xfr_complete); + //wait_for_completion(&dev->xfr_complete); davinci_i2c_reset_ctrl(dev, 0); } else if (val == CPUFREQ_POSTCHANGE) {