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Mon, 27 Nov 2023 23:16:22 -0800 From: Mohan Kumar To: , , , CC: , , , , , , Mohan Kumar Subject: [RESEND PATCH V2 0/2] Support dma channel mask Date: Tue, 28 Nov 2023 12:46:13 +0530 Message-ID: <20231128071615.31447-1-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F6:EE_|SA0PR12MB7075:EE_ X-MS-Office365-Filtering-Correlation-Id: c4c56db5-9fec-4e75-bf57-08dbefe1f168 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OnrGHZXs/+ZWc/tRSVtSHvaqlW4AGbZfrKhEi92RQ9x1VOfa8PzkmraAVpOgpYyzjK71nlSZC/kCLv+CEDcmRmEduvs6R5mVl/mdxBcN9tCw54Cdqz9MA4ng7Dla05ouTBM3m4cHTlhc0bebT8rr6yCTqcrDiZc3GllTnsyiPlSf1ANqgGm1XHWeDyy2DOOlmSo1xctEuxyVozx/kjENUPritb7c2kwLxdNMiitYOhz4gFc7Uim4Fxei+rz2juaa7msCFGxw59X6xqJYR8+KuWeID0oDvRrMavJb5HgSmcJJs1MrgGioLSvkEkjE8Mr1VBljw+v8KcnoyMcm71FGiz7VDjLWJ6nyFyTRlvHBaZvZDNfy3Pg+WqqtPlzJidTL9O8/GnWdo28ZVxBzLlnGq9mu4TnKuosnq2oAaAP4BdeDeHYzswWBAYX+66tpeLhRn0ufz3AFvCATCHnkaTdi8aup9zGCFak/OlNwWQf2VRF0yvSs1hRWOfYwVPwdrj9QS4cIXzMVtWY9/fqyaNz2qExBcsNa0dLQ+VAyWwPPBmA1SYLxhMZ3ZWnmcYd30ANH/Zfpj5LGk9HouAJKhPsm9xQTcwpJ7Y2ZVuqAiCGLnc96T4b6PbgLfiIC6OH/bnmLVHBboivuB8DsxfFnaIVMKzD43oyzAKEeHLNRfK+r2K6DcFK/3K+VriupXtjdiIYr51TvZ4z6NbTz6OGs/J0ZssN78NaY+ndHkKdIL+OWKT1WcSWA/D3wtgHN1K1jBNn4 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(136003)(346002)(396003)(39860400002)(230922051799003)(451199024)(1800799012)(82310400011)(186009)(64100799003)(36840700001)(46966006)(40470700004)(83380400001)(40480700001)(47076005)(356005)(7636003)(336012)(4326008)(82740400003)(70206006)(8936002)(426003)(7696005)(5660300002)(54906003)(316002)(70586007)(110136005)(8676002)(36860700001)(478600001)(86362001)(41300700001)(2906002)(4744005)(36756003)(6666004)(26005)(107886003)(1076003)(2616005)(40460700003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2023 07:16:29.8973 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4c56db5-9fec-4e75-bf57-08dbefe1f168 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7075 To reserve the dma channel using dma-channel-mask property for Tegra platforms. Mohan Kumar (2): dt-bindings: dma: Add dma-channel-mask to nvidia,tegra210-adma dmaengine: tegra210-adma: Support dma-channel-mask property .../bindings/dma/nvidia,tegra210-adma.yaml | 3 ++ drivers/dma/tegra210-adma.c | 35 +++++++++++++++++-- 2 files changed, 36 insertions(+), 2 deletions(-)