From patchwork Tue Feb 4 20:42:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 3579181 X-Patchwork-Delegate: vinod.koul@intel.com Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4AB6F9F2F5 for ; Tue, 4 Feb 2014 20:43:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 751EF2018B for ; Tue, 4 Feb 2014 20:43:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 94DB12016C for ; Tue, 4 Feb 2014 20:43:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755113AbaBDUnD (ORCPT ); Tue, 4 Feb 2014 15:43:03 -0500 Received: from smtp.codeaurora.org ([198.145.11.231]:47823 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755017AbaBDUms (ORCPT ); Tue, 4 Feb 2014 15:42:48 -0500 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 6C54413F031; Tue, 4 Feb 2014 20:42:48 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 5AF2113F291; Tue, 4 Feb 2014 20:42:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: agross@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C8CAB13F031; Tue, 4 Feb 2014 20:42:47 +0000 (UTC) From: Andy Gross To: Vinod Koul , Dan Williams , dmaengine@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Andy Gross Subject: [Patch v5 2/2] dmaengine: qcom_bam_dma: Add device tree binding Date: Tue, 4 Feb 2014 14:42:36 -0600 Message-Id: <1391546556-27702-3-git-send-email-agross@codeaurora.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1391546556-27702-1-git-send-email-agross@codeaurora.org> References: <1391546556-27702-1-git-send-email-agross@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device tree binding support for the QCOM BAM DMA driver. Signed-off-by: Andy Gross Acked-by: Kumar Gala --- .../devicetree/bindings/dma/qcom_bam_dma.txt | 48 ++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt new file mode 100644 index 0000000..86344f1 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt @@ -0,0 +1,48 @@ +QCOM BAM DMA controller + +Required properties: +- compatible: Must be "qcom,bam-v1.4.0" for MSM8974 V1 + Must be "qcom,bam-v1.4.1" for MSM8974 V2 +- reg: Address range for DMA registers +- interrupts: single interrupt for this controller +- #dma-cells: must be <1> +- clocks: required clock +- clock-names: name of clock +- qcom,ee : indicates the active Execution Environment identifier (0-7) + +Example: + + uart-bam: dma@f9984000 = { + compatible = "qcom,bam-v1.4.1"; + reg = <0xf9984000 0x15000>; + interrupts = <0 94 0>; + clocks = <&gcc GCC_BAM_DMA_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + +Client: +Required properties: +- dmas: List of dma channel requests +- dma-names: Names of aforementioned requested channels + +Clients must use the format described in the dma.txt file, using a two cell +specifier for each channel. + +The three cells in order are: + 1. A phandle pointing to the DMA controller + 2. The channel number + +Example: + serial@f991e000 { + compatible = "qcom,msm-uart"; + reg = <0xf991e000 0x1000> + <0xf9944000 0x19000>; + interrupts = <0 108 0>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + + dmas = <&uart-bam 0>, <&uart-bam 1>; + dma-names = "rx", "tx"; + };