diff mbox

[v2,8/8] ARM: shmobile: r8a7791: Add DMAC devices to DT

Message ID 1405727425-6237-9-git-send-email-laurent.pinchart+renesas@ideasonboard.com (mailing list archive)
State Superseded
Delegated to: Vinod Koul
Headers show

Commit Message

Laurent Pinchart July 18, 2014, 11:50 p.m. UTC
Instantiate the two system DMA controllers in the r8a7791 device tree.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

---

Changes since v1:

- Remove ch15 from interrupt names
---
 arch/arm/boot/dts/r8a7791.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

Comments

Simon Horman Aug. 8, 2014, 2:19 a.m. UTC | #1
On Sat, Jul 19, 2014 at 01:50:25AM +0200, Laurent Pinchart wrote:
> Instantiate the two system DMA controllers in the r8a7791 device tree.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Thanks. As the bindings have been merged I have queued up this patch for
v3.18.

> ---
> 
> Changes since v1:
> 
> - Remove ch15 from interrupt names
> ---
>  arch/arm/boot/dts/r8a7791.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 60 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
> index 56841d3..9cbe5f8 100644
> --- a/arch/arm/boot/dts/r8a7791.dtsi
> +++ b/arch/arm/boot/dts/r8a7791.dtsi
> @@ -238,6 +238,66 @@
>  			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
>  	};
>  
> +	dmac0: dma-controller@e6700000 {
> +		compatible = "renesas,rcar-dmac";
> +		reg = <0 0xe6700000 0 0x20000>;
> +		interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
> +			      0 200 IRQ_TYPE_LEVEL_HIGH
> +			      0 201 IRQ_TYPE_LEVEL_HIGH
> +			      0 202 IRQ_TYPE_LEVEL_HIGH
> +			      0 203 IRQ_TYPE_LEVEL_HIGH
> +			      0 204 IRQ_TYPE_LEVEL_HIGH
> +			      0 205 IRQ_TYPE_LEVEL_HIGH
> +			      0 206 IRQ_TYPE_LEVEL_HIGH
> +			      0 207 IRQ_TYPE_LEVEL_HIGH
> +			      0 208 IRQ_TYPE_LEVEL_HIGH
> +			      0 209 IRQ_TYPE_LEVEL_HIGH
> +			      0 210 IRQ_TYPE_LEVEL_HIGH
> +			      0 211 IRQ_TYPE_LEVEL_HIGH
> +			      0 212 IRQ_TYPE_LEVEL_HIGH
> +			      0 213 IRQ_TYPE_LEVEL_HIGH
> +			      0 214 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "error",
> +				"ch0", "ch1", "ch2", "ch3",
> +				"ch4", "ch5", "ch6", "ch7",
> +				"ch8", "ch9", "ch10", "ch11",
> +				"ch12", "ch13", "ch14";
> +		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
> +		clock-names = "fck";
> +		#dma-cells = <1>;
> +		dma-channels = <15>;
> +	};
> +
> +	dmac1: dma-controller@e6720000 {
> +		compatible = "renesas,rcar-dmac";
> +		reg = <0 0xe6720000 0 0x20000>;
> +		interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
> +			      0 216 IRQ_TYPE_LEVEL_HIGH
> +			      0 217 IRQ_TYPE_LEVEL_HIGH
> +			      0 218 IRQ_TYPE_LEVEL_HIGH
> +			      0 219 IRQ_TYPE_LEVEL_HIGH
> +			      0 308 IRQ_TYPE_LEVEL_HIGH
> +			      0 309 IRQ_TYPE_LEVEL_HIGH
> +			      0 310 IRQ_TYPE_LEVEL_HIGH
> +			      0 311 IRQ_TYPE_LEVEL_HIGH
> +			      0 312 IRQ_TYPE_LEVEL_HIGH
> +			      0 313 IRQ_TYPE_LEVEL_HIGH
> +			      0 314 IRQ_TYPE_LEVEL_HIGH
> +			      0 315 IRQ_TYPE_LEVEL_HIGH
> +			      0 316 IRQ_TYPE_LEVEL_HIGH
> +			      0 317 IRQ_TYPE_LEVEL_HIGH
> +			      0 318 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "error",
> +				"ch0", "ch1", "ch2", "ch3",
> +				"ch4", "ch5", "ch6", "ch7",
> +				"ch8", "ch9", "ch10", "ch11",
> +				"ch12", "ch13", "ch14";
> +		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
> +		clock-names = "fck";
> +		#dma-cells = <1>;
> +		dma-channels = <15>;
> +	};
> +
>  	/* The memory map in the User's Manual maps the cores to bus numbers */
>  	i2c0: i2c@e6508000 {
>  		#address-cells = <1>;
> -- 
> 1.8.5.5
> 
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diff mbox

Patch

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 56841d3..9cbe5f8 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -238,6 +238,66 @@ 
 			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	dmac0: dma-controller@e6700000 {
+		compatible = "renesas,rcar-dmac";
+		reg = <0 0xe6700000 0 0x20000>;
+		interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
+			      0 200 IRQ_TYPE_LEVEL_HIGH
+			      0 201 IRQ_TYPE_LEVEL_HIGH
+			      0 202 IRQ_TYPE_LEVEL_HIGH
+			      0 203 IRQ_TYPE_LEVEL_HIGH
+			      0 204 IRQ_TYPE_LEVEL_HIGH
+			      0 205 IRQ_TYPE_LEVEL_HIGH
+			      0 206 IRQ_TYPE_LEVEL_HIGH
+			      0 207 IRQ_TYPE_LEVEL_HIGH
+			      0 208 IRQ_TYPE_LEVEL_HIGH
+			      0 209 IRQ_TYPE_LEVEL_HIGH
+			      0 210 IRQ_TYPE_LEVEL_HIGH
+			      0 211 IRQ_TYPE_LEVEL_HIGH
+			      0 212 IRQ_TYPE_LEVEL_HIGH
+			      0 213 IRQ_TYPE_LEVEL_HIGH
+			      0 214 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				"ch0", "ch1", "ch2", "ch3",
+				"ch4", "ch5", "ch6", "ch7",
+				"ch8", "ch9", "ch10", "ch11",
+				"ch12", "ch13", "ch14";
+		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
+		clock-names = "fck";
+		#dma-cells = <1>;
+		dma-channels = <15>;
+	};
+
+	dmac1: dma-controller@e6720000 {
+		compatible = "renesas,rcar-dmac";
+		reg = <0 0xe6720000 0 0x20000>;
+		interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
+			      0 216 IRQ_TYPE_LEVEL_HIGH
+			      0 217 IRQ_TYPE_LEVEL_HIGH
+			      0 218 IRQ_TYPE_LEVEL_HIGH
+			      0 219 IRQ_TYPE_LEVEL_HIGH
+			      0 308 IRQ_TYPE_LEVEL_HIGH
+			      0 309 IRQ_TYPE_LEVEL_HIGH
+			      0 310 IRQ_TYPE_LEVEL_HIGH
+			      0 311 IRQ_TYPE_LEVEL_HIGH
+			      0 312 IRQ_TYPE_LEVEL_HIGH
+			      0 313 IRQ_TYPE_LEVEL_HIGH
+			      0 314 IRQ_TYPE_LEVEL_HIGH
+			      0 315 IRQ_TYPE_LEVEL_HIGH
+			      0 316 IRQ_TYPE_LEVEL_HIGH
+			      0 317 IRQ_TYPE_LEVEL_HIGH
+			      0 318 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				"ch0", "ch1", "ch2", "ch3",
+				"ch4", "ch5", "ch6", "ch7",
+				"ch8", "ch9", "ch10", "ch11",
+				"ch12", "ch13", "ch14";
+		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
+		clock-names = "fck";
+		#dma-cells = <1>;
+		dma-channels = <15>;
+	};
+
 	/* The memory map in the User's Manual maps the cores to bus numbers */
 	i2c0: i2c@e6508000 {
 		#address-cells = <1>;