From patchwork Tue Aug 5 11:39:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srikanth Thokala X-Patchwork-Id: 4678341 X-Patchwork-Delegate: vinod.koul@intel.com Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3AA849F373 for ; Tue, 5 Aug 2014 11:40:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5AE5120120 for ; Tue, 5 Aug 2014 11:40:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 52D552014A for ; Tue, 5 Aug 2014 11:40:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752866AbaHELj7 (ORCPT ); Tue, 5 Aug 2014 07:39:59 -0400 Received: from mail-qg0-f46.google.com ([209.85.192.46]:61546 "EHLO mail-qg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752850AbaHELj7 (ORCPT ); Tue, 5 Aug 2014 07:39:59 -0400 Received: by mail-qg0-f46.google.com with SMTP id z60so799951qgd.19 for ; Tue, 05 Aug 2014 04:39:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=f9OBEBTz35ezqeKl7i7Z3IoJA/flhhCjI9sAVPOLGRs=; b=KyOGVb5ruDSRjPz1fErd5FM28rjOHrSANcLiP2LBdcq2JNUmikT6fNCeNqaY2Tx9rL umhIkB7enE9DsV4H+ns8SRuE1dLSxM0vbq2MZGITWkZMjBTmMpECkacOIJbtDvryyPWc bOjZs77lX1hpSU6ScfouweIA5VDkJFgOtFCHfZLxGjaeY4RTLsHhcHU9J4EBVRYLSuVs FFxeFCDDRVA1DBcjOr/UUQQc1daQMxdWvt6na3jwTbBrMXbQfozTqORSaS+buD4q2DJG yJ+acr5gUniiEQIA9UEOT7a4mHqb+/j5uPTCwiE9vRcDRHu1tzkzt5Mrt9nzT1fAnvXz KckQ== X-Received: by 10.224.137.65 with SMTP id v1mr4563800qat.53.1407238798075; Tue, 05 Aug 2014 04:39:58 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id i18sm2641051qar.29.2014.08.05.04.39.55 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 05 Aug 2014 04:39:56 -0700 (PDT) From: Srikanth Thokala To: vinod.koul@intel.com, dan.j.williams@intel.com, michal.simek@xilinx.com, grant.likely@linaro.org, robh+dt@kernel.org, levex@linux.com, jassisinghbrar@gmail.com Cc: linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, anirudh@xilinx.com, svemula@xilinx.com, Srikanth Thokala Subject: [PATCH v2 1/2] dma: Add Xilinx Central DMA DT Binding Documentation Date: Tue, 5 Aug 2014 17:09:50 +0530 Message-Id: <1407238791-3370-1-git-send-email-sthokal@xilinx.com> X-Mailer: git-send-email 1.7.9.5 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Device-tree binding documentation of Xilinx Central DMA Engine Signed-off-by: Srikanth Thokala --- Changes in v2: - Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description to match the implementation. --- .../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54 ++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt new file mode 100644 index 0000000..b04f76b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt @@ -0,0 +1,54 @@ +Xilinx AXI CDMA engine, it does transfers between memory-mapped source +address and a memory-mapped destination address. + +Required properties: +- compatible: Should be "xlnx,axi-cdma-1.00.a" +- #dma-cells: Should be <1>, see "dmas" property below +- reg: Should contain cdma registers location and length. +- dma-channel child node: Should have only one channel + +Optional properties: +- xlnx,include-sg: Tells whether configured for Scatter-mode in + the hardware. + +Required child node properties: +- compatible: It should be "xlnx,axi-cdma-channel". +- interrupts: Should contain per channel CDMA interrupts. +- xlnx,datawidth: Should contain the stream data width, take values + {32,64...1024}. + +Option child node properties: +- xlnx,include-dre: Tells whether hardware is configured for Data + Realignment Engine. + +Example: +++++++++ + +axi_cdma_0: axicdma@7e200000 { + compatible = "xlnx,axi-cdma-1.00.a"; + #dma_cells = <1>; + reg = < 0x7e200000 0x10000 >; + dma-channel@7e200000 { + compatible = "xlnx,axi-cdma-channel"; + interrupts = < 0 55 4 >; + xlnx,datawidth = <0x40>; + } ; +} ; + + +* DMA client + +Required properties: +- dmas: a list of <[Central DMA device phandle] [Channel ID]> pairs, + where Channel ID is '0' for write/tx and '1' for read/rx + channel. +- dma-names: a list of DMA channel names, one per "dmas" entry + +Example: +++++++++ + +cdmatest_0: cdmatest@0 { + compatible ="xlnx,axi-cdma-test-1.00.a"; + dmas = <&axi_cdma_0 0>; + dma-names = "cdma0"; +} ;