From patchwork Fri Sep 12 07:37:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 4892321 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C493E9F537 for ; Fri, 12 Sep 2014 07:32:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3739F20148 for ; Fri, 12 Sep 2014 07:38:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3E80520260 for ; Fri, 12 Sep 2014 07:37:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753394AbaILHh7 (ORCPT ); Fri, 12 Sep 2014 03:37:59 -0400 Received: from mail-wi0-f179.google.com ([209.85.212.179]:33549 "EHLO mail-wi0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753280AbaILHh6 (ORCPT ); Fri, 12 Sep 2014 03:37:58 -0400 Received: by mail-wi0-f179.google.com with SMTP id hi2so84897wib.6 for ; Fri, 12 Sep 2014 00:37:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=gJM6Lwu4C4yrDF4JhZbstheDpxyF8eL3lrZMiPDTC4Q=; b=JXMzXKAk1r5+RaChCeY0LiY81chKm8BLWeluozEAUluaa4OlDGIc50jYraf+nzowif +AbteSKQ5zDEUpovcBX6amLbkc7thS4N5tBk09VEemhNTvMTjK4PFvvC5VkQYFpUo8x3 PCHZYuwGzNCn5udgrnjZIX5kb4qPp4SYxvONj6H26BmmPQ6BwTsae7Q5MV14tXOVz+SZ xQfFZS1wmKLfbqjejL70asZDDAZA5ocFcAPictAi3B2pwwJ8hz7B2qLneWftTPHjBY1y rlKYYHDbbeUC8lvkI7xhF8l0B5VSDK3ivBRikPujtAV18/ZJi6Yt8fs3NJD3LnTh9aMa BasA== X-Gm-Message-State: ALoCoQlQkNBzNoV6NTmDH+b8tWAFGE9aTitSh86hd9b3EKY8EiWax0TRgLsprwizOIDD9BmikjU3 X-Received: by 10.194.205.196 with SMTP id li4mr8443474wjc.46.1410507477248; Fri, 12 Sep 2014 00:37:57 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id wr8sm3610466wjb.20.2014.09.12.00.37.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Sep 2014 00:37:56 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org, Vinod Koul , Roland Stigge , Arnd Bergmann Cc: Russell King , Dan Williams , Linus Walleij Subject: [PATCH 4/4] ARM: nomadik: add DMA support Date: Fri, 12 Sep 2014 09:37:52 +0200 Message-Id: <1410507472-32530-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds DMA controller entries for the two PL08x blocks on the Nomadik, assigns the fixed signal names, and defines channels for UART and MMC/SD. Tested on the S8815 USB dongle. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 296 +++++++++++++++++++++++++++++ 1 file changed, 296 insertions(+) diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index dbcf521b017f..8ffe68d9f670 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -794,6 +794,10 @@ clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart0_default_mux>; + dmas = <&dmac0 14>, + <&dmac0 15>; + dma-names = "rx", "tx"; + }; uart1: uart@101fb000 { @@ -805,6 +809,9 @@ clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart1_default_mux>; + dmas = <&dmac1 22>, + <&dmac1 23>; + dma-names = "rx", "tx"; }; uart2: uart@101f2000 { @@ -848,6 +855,295 @@ pinctrl-names = "default"; pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; vmmc-supply = <&vmmc_regulator>; + dmas = <&dmac1 21>; + dma-names = "rx"; + }; + + dmac0: dma-controller@10130000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <15>; + clocks = <&hclkdma0>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <1>; + /* Assignments for the 32 channels */ + saa0@dmac0 { + signal = "saa0"; + bus-interface-ahb1; + }; + saa1@dmac0 { + signal = "saa1"; + bus-interface-ahb1; + }; + saa2@dmac0 { + signal = "saa2"; + bus-interface-ahb1; + }; + saa3@dmac0 { + signal = "saa3"; + bus-interface-ahb1; + }; + saa4@dmac0 { + signal = "saa4"; + bus-interface-ahb1; + }; + saa5@dmac0 { + signal = "saa5"; + bus-interface-ahb1; + }; + saa6@dmac0 { + signal = "saa6"; + bus-interface-ahb1; + }; + saa7@dmac0 { + signal = "saa7"; + bus-interface-ahb1; + }; + unused@dmac0 { + signal = "unused"; + bus-interface-ahb1; + }; + fir@dmac0 { + signal = "firdatxrx"; + bus-interface-ahb1; + }; + msp0rx@dmac0 { + signal = "msp0rx"; + bus-interface-ahb1; + }; + msp0tx@dmac0 { + signal = "msp0tx"; + bus-interface-ahb1; + }; + ssprx@dmac0 { + signal = "ssprx"; + bus-interface-ahb1; + }; + ssptx@dmac0 { + signal = "ssptx"; + bus-interface-ahb1; + }; + uart0rx@dmac0 { + signal = "uart0rx"; + bus-interface-ahb1; + }; + uart0tx@dmac0 { + signal = "uart0tx"; + bus-interface-ahb1; + }; + hsirxch0@dmac0 { + signal = "hsirxch0"; + bus-interface-ahb1; + }; + hsirxch1@dmac0 { + signal = "hsirxch1"; + bus-interface-ahb1; + }; + hsirxch2@dmac0 { + signal = "hsirxch2"; + bus-interface-ahb1; + }; + hsirxch3@dmac0 { + signal = "hsirxch3"; + bus-interface-ahb1; + }; + hsirxch4@dmac0 { + signal = "hsirxch4"; + bus-interface-ahb1; + }; + hsirxch5@dmac0 { + signal = "hsirxch5"; + bus-interface-ahb1; + }; + hsirxch6@dmac0 { + signal = "hsirxch6"; + bus-interface-ahb1; + }; + hsirxch7@dmac0 { + signal = "hsirxch7"; + bus-interface-ahb1; + }; + hsitxch0@dmac0 { + signal = "hsitxch0"; + bus-interface-ahb1; + }; + hsitxch1@dmac0 { + signal = "hsitxch1"; + bus-interface-ahb1; + }; + hsitxch2@dmac0 { + signal = "hsitxch2"; + bus-interface-ahb1; + }; + hsitxch3@dmac0 { + signal = "hsitxch3"; + bus-interface-ahb1; + }; + hsitxch4@dmac0 { + signal = "hsitxch4"; + bus-interface-ahb1; + }; + hsitxch5@dmac0 { + signal = "hsitxch5"; + bus-interface-ahb1; + }; + hsitxch6@dmac0 { + signal = "hsitxch6"; + bus-interface-ahb1; + }; + hsitxch7@dmac0 { + signal = "hsitxch7"; + bus-interface-ahb1; + }; + }; + dmac1: dma-controller@10150000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10150000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <13>; + clocks = <&hclkdma1>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <1>; + /* Assignments for the 32 channels */ + saa0@dmac1 { + signal = "saa0"; + bus-interface-ahb1; + }; + saa1@dmac1 { + signal = "saa1"; + bus-interface-ahb1; + }; + saa2@dmac1 { + signal = "saa2"; + bus-interface-ahb1; + }; + saa3@dmac1 { + signal = "saa3"; + bus-interface-ahb1; + }; + saa4@dmac1 { + signal = "saa4"; + bus-interface-ahb1; + }; + saa5@dmac1 { + signal = "saa5"; + bus-interface-ahb1; + }; + saa6@dmac1 { + signal = "saa6"; + bus-interface-ahb1; + }; + saa7@dmac1 { + signal = "saa7"; + bus-interface-ahb1; + }; + unused@dmac1 { + signal = "unused"; + bus-interface-ahb1; + }; + fir@dmac1 { + signal = "firdatxrx"; + bus-interface-ahb1; + }; + msp0rx@dmac1 { + signal = "msp0rx"; + bus-interface-ahb1; + }; + msp0tx@dmac1 { + signal = "msp0tx"; + bus-interface-ahb1; + }; + ssprx@dmac1 { + signal = "ssprx"; + bus-interface-ahb1; + }; + ssptx@dmac1 { + signal = "ssptx"; + bus-interface-ahb1; + }; + uart0rx@dmac1 { + signal = "uart0rx"; + bus-interface-ahb1; + }; + uart0tx@dmac1 { + signal = "uart0tx"; + bus-interface-ahb1; + }; + tdesin@dmac1 { + signal = "tdesin"; + bus-interface-ahb1; + }; + tdesout@dmac1 { + signal = "tdesout"; + bus-interface-ahb1; + }; + i2c1rxtx@dmac1 { + signal = "i2c1rxtx"; + bus-interface-ahb1; + }; + i2c0rxtx@dmac1 { + signal = "i2c0rxtx"; + bus-interface-ahb1; + }; + sha1@dmac1 { + signal = "sha1"; + bus-interface-ahb1; + }; + sdirxtx@dmac1 { + signal = "sdirxtx"; + bus-interface-ahb1; + }; + uart1rxdmac1 { + signal = "uart1rx"; + bus-interface-ahb1; + }; + uart1tx@dmac1 { + signal = "uart1tx"; + bus-interface-ahb1; + }; + usbotg0@dmac1 { + signal = "usbotg0"; + bus-interface-ahb1; + }; + usbotg1@dmac1 { + signal = "usbotg1"; + bus-interface-ahb1; + }; + usbotg2@dmac1 { + signal = "usbotg2"; + bus-interface-ahb1; + }; + usbotg3@dmac1 { + signal = "usbotg3"; + bus-interface-ahb1; + }; + usbotg4@dmac1 { + signal = "usbotg4"; + bus-interface-ahb1; + }; + usbotg5@dmac1 { + signal = "usbotg5"; + bus-interface-ahb1; + }; + usbotg6@dmac1 { + signal = "usbotg6"; + bus-interface-ahb1; + }; + usbotg7@dmac1 { + signal = "usbotg7"; + bus-interface-ahb1; + }; }; }; };