From patchwork Mon Sep 22 13:22:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ludovic Desroches X-Patchwork-Id: 4947761 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id ED8BD9F313 for ; Mon, 22 Sep 2014 13:23:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 292D220160 for ; Mon, 22 Sep 2014 13:23:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E45C6200D9 for ; Mon, 22 Sep 2014 13:23:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753932AbaIVNXM (ORCPT ); Mon, 22 Sep 2014 09:23:12 -0400 Received: from eusmtp01.atmel.com ([212.144.249.242]:22826 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753880AbaIVNXM (ORCPT ); Mon, 22 Sep 2014 09:23:12 -0400 Received: from ibiza.corp.atmel.com (10.161.101.13) by eusmtp01.atmel.com (10.161.101.30) with Microsoft SMTP Server id 14.2.347.0; Mon, 22 Sep 2014 15:23:09 +0200 From: Ludovic Desroches To: , , CC: , , , , , , , , , Ludovic Desroches Subject: [PATCH v5 2/3] ARM: dts: at_xdmac: add bindings documentation Date: Mon, 22 Sep 2014 15:22:17 +0200 Message-ID: <1411392138-5014-3-git-send-email-ludovic.desroches@atmel.com> X-Mailer: git-send-email 2.0.3 In-Reply-To: <1411392138-5014-1-git-send-email-ludovic.desroches@atmel.com> References: <1411392138-5014-1-git-send-email-ludovic.desroches@atmel.com> MIME-Version: 1.0 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add bindings documentation for the new Atmel DMA controller (XDMAC) introduced with SAMA5D4. Signed-off-by: Ludovic Desroches Acked-by: Nicolas Ferre --- .../devicetree/bindings/dma/atmel-xdma.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/atmel-xdma.txt diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt new file mode 100644 index 0000000..ae587ad --- /dev/null +++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt @@ -0,0 +1,50 @@ +* Atmel Extensible Direct Memory Access Controller (XDMAC) + +* XDMA Controller +Required properties: +- compatible: Should be "atmel,-dma". + compatible description: + - sama5d4: first SoC adding the XDMAC +- reg: Should contain DMA registers location and length. +- interrupts: Should contain DMA interrupt. +- #dma-cells: Must be <2>, used to represent the number of integer cells in +the dmas property of client devices. + - The 1st cell specifies the memory interface (16 most significant bits) and + the peripheral interface (16 less significant bits) to use. + - The 2nd cell specifies the channel configuration register: + - bit 30-24: PERID, peripheral identifier. + +Example: + +dma1: dma-controller@f0004000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0004000 0x200>; + interrupts = <50 4 0>; + #dma-cells = <2>; +}; + + +* DMA clients +DMA clients connected to the Atmel XDMA controller must use the format +described in the dma.txt file, using a two-cell specifier for each channel. +The three cells in order are: +1. A phandle pointing to the DMA controller. +2. The memory interface (16 most significant bits), the peripheral interface +(16 less significant bits). +3. Channel configuration register. Configurable fields are: + - bit 30-24: PERID, peripheral identifier. + +Example: + +i2c2: i2c@f8024000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8024000 0x4000>; + interrupts = <34 4 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(6)>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) + AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; +};