From patchwork Fri Nov 7 18:05:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jon Medhurst (Tixy)" X-Patchwork-Id: 5254971 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9A4869F387 for ; Fri, 7 Nov 2014 18:40:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 77E0020122 for ; Fri, 7 Nov 2014 18:40:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9DCB620121 for ; Fri, 7 Nov 2014 18:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753083AbaKGSke (ORCPT ); Fri, 7 Nov 2014 13:40:34 -0500 Received: from queue01c.mail.zen.net.uk ([212.23.3.237]:36324 "EHLO queue01c.mail.zen.net.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753095AbaKGSkP (ORCPT ); Fri, 7 Nov 2014 13:40:15 -0500 Received: from [212.23.1.1] (helo=smarthost01a.mail.zen.net.uk) by queue01c.mail.zen.net.uk with esmtp (Exim 4.72) (envelope-from ) id 1Xmnvg-0007lq-7o; Fri, 07 Nov 2014 18:06:36 +0000 Received: from [82.69.122.217] (helo=plug1) by smarthost01a.mail.zen.net.uk with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1XmnvC-0000ZR-Ma; Fri, 07 Nov 2014 18:06:06 +0000 Received: from linaro1 ([192.168.2.110] helo=linaro1.home) by plug1 with esmtp (Exim 4.80) (envelope-from ) id 1Xmnv9-0002Dg-5E; Fri, 07 Nov 2014 18:06:03 +0000 Received: from tixy by linaro1.home with local (Exim 4.84) (envelope-from ) id 1Xmnv9-0007dv-3g; Fri, 07 Nov 2014 18:06:03 +0000 From: Jon Medhurst To: Vinod Koul , Dan Williams , dmaengine@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] dma: pl330: Align DMA memcpy operations to MFIFO width Date: Fri, 7 Nov 2014 18:05:17 +0000 Message-Id: <1415383518-29327-2-git-send-email-tixy@linaro.org> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1415383518-29327-1-git-send-email-tixy@linaro.org> References: <1415383518-29327-1-git-send-email-tixy@linaro.org> X-Originating-smarthost01a-IP: [82.69.122.217] Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The algorithm used for programming the DMA Controller doesn't take into consideration the requirements of transfers that are not aligned to the bus width. This failure may result in DMA transferring one too few MFIFO entries (so too few bytes are copied) or the DMA trying to write one too many MFIFO entries and hanging because this is never provided. See "MFIFO Usage Overview" chapter in the the TRM for "CoreLink DMA Controller DMA-330", Revision r1p1. We work around these shortcomings by making sure we pick a burst size and length which ensures no bursts straddle an MFIFO entry. Signed-off-by: Jon Medhurst --- drivers/dma/pl330.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 4839bfa..8f869ec 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -2459,8 +2459,13 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, /* Select max possible burst size */ burst = pl330->pcfg.data_bus_width / 8; + /* + * Make sure we use a burst size that aligns with all the memcpy + * parameters because our DMA programming algorithm doesn't cope with + * transfers which straddle an entry in the DMA device's MFIFO. + */ while (burst > 1) { - if (!(len % burst)) + if (!((src | dst | len) % burst)) break; burst /= 2; } @@ -2469,6 +2474,13 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, while (burst != (1 << desc->rqcfg.brst_size)) desc->rqcfg.brst_size++; + /* + * If burst size is smaller than bus width then make sure we only + * transfer one at a time to avoid a burst stradling an MFIFO entry. + */ + if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) + desc->rqcfg.brst_len = 1; + desc->rqcfg.brst_len = get_burst_len(desc, len); desc->txd.flags = flags;