From patchwork Wed Aug 5 05:23:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 6946201 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8EE2AC05AC for ; Wed, 5 Aug 2015 05:23:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BAC9A204D5 for ; Wed, 5 Aug 2015 05:23:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D6AE720426 for ; Wed, 5 Aug 2015 05:23:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750905AbbHEFXk (ORCPT ); Wed, 5 Aug 2015 01:23:40 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:36318 "EHLO mail-pd0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750738AbbHEFXk (ORCPT ); Wed, 5 Aug 2015 01:23:40 -0400 Received: by pdco4 with SMTP id o4so13644568pdc.3 for ; Tue, 04 Aug 2015 22:23:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=bekAuguKVlfhjG/f8MWVeKYXVc9ntonMhMuElNXS9vA=; b=bMcjc/Z9Rx68l3Wzie9117VZuVTohacLuT4GreFg0U7CVTJkdfmjR3dbsVw/AGyqBK UUmH7ubP1kRMIqGwMbvtGhaJkIq5eHkKKmj6ncBQ6apPOOOiSz4oyZQD9iuaHCvxGWJ0 lVSR1DIZGWcVzRTb186qU62XC1ccfXCrX/cpUzBBumG6LMyaI3g8z+AxRxA9nbI81hzI /eLsZH6qhXt/0p6jMiWkmCkGW2dG+Pw97sDDZJcZ0p/W3w9JhtB5lkDvJ/xRAqsrAbnj 61sDNWQcVpjxioU3sr1hkTFLhCqrR9wesSbFGHH8CFB7yRokF+hiiNqTFutI9YyTPpgg sfpg== X-Gm-Message-State: ALoCoQndprr0eUUYZtqCjUpLIRocqc1e5wFoYCI9Wp6OoQ12+wW797EneJxfifL94krjqjeZwaY+ X-Received: by 10.70.100.201 with SMTP id fa9mr15807116pdb.34.1438752219584; Tue, 04 Aug 2015 22:23:39 -0700 (PDT) Received: from localhost.localdomain ([43.252.215.166]) by smtp.gmail.com with ESMTPSA id to5sm1228599pac.33.2015.08.04.22.23.35 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Aug 2015 22:23:38 -0700 (PDT) From: Jun Nie To: vinod.koul@intel.com, dmaengine@vger.kernel.org Cc: shawn.guo@linaro.org, wan.zhijun@zte.com.cn, jason.liu@linaro.org, Jun Nie Subject: [PATCH v2 1/2] dmaengine: zxdma: Fix data width bug Date: Wed, 5 Aug 2015 13:23:26 +0800 Message-Id: <1438752207-12244-1-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Align src and dst width to fix data alignment issue as trailing single transaction that does not fill a full burst require identical src/dst data width. Burst length limitation can be addressed well too. Signed-off-by: Jun Nie --- drivers/dma/zx296702_dma.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/dma/zx296702_dma.c b/drivers/dma/zx296702_dma.c index 0d55c8f..103691c6 100644 --- a/drivers/dma/zx296702_dma.c +++ b/drivers/dma/zx296702_dma.c @@ -476,15 +476,16 @@ static int zx_pre_config(struct zx_dma_chan *c, enum dma_transfer_direction dir) c->dev_addr = cfg->dst_addr; /* dst len is calculated from src width, len and dst width. * We need make sure dst len not exceed MAX LEN. + * Trailing single transaction that does not fill a full + * burst also require identical src/dst data width. */ dst_width = zx_dma_burst_width(cfg->dst_addr_width); - maxburst = cfg->dst_maxburst * cfg->dst_addr_width - / DMA_SLAVE_BUSWIDTH_8_BYTES; + maxburst = cfg->dst_maxburst; maxburst = maxburst < ZX_MAX_BURST_LEN ? maxburst : ZX_MAX_BURST_LEN; c->ccfg = ZX_DST_FIFO_MODE | ZX_CH_ENABLE | ZX_SRC_BURST_LEN(maxburst - 1) - | ZX_SRC_BURST_WIDTH(ZX_DMA_WIDTH_64BIT) + | ZX_SRC_BURST_WIDTH(dst_width) | ZX_DST_BURST_WIDTH(dst_width); break; case DMA_DEV_TO_MEM: @@ -496,7 +497,7 @@ static int zx_pre_config(struct zx_dma_chan *c, enum dma_transfer_direction dir) c->ccfg = ZX_SRC_FIFO_MODE | ZX_CH_ENABLE | ZX_SRC_BURST_LEN(maxburst - 1) | ZX_SRC_BURST_WIDTH(src_width) - | ZX_DST_BURST_WIDTH(ZX_DMA_WIDTH_64BIT); + | ZX_DST_BURST_WIDTH(src_width); break; default: return -EINVAL;