From patchwork Sun Jan 24 19:21:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TcOlbnMgUnVsbGfDpXJk?= X-Patchwork-Id: 8101171 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 80E32BEEE5 for ; Sun, 24 Jan 2016 19:27:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 989D320380 for ; Sun, 24 Jan 2016 19:27:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B38A2021A for ; Sun, 24 Jan 2016 19:27:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753677AbcAXTZC (ORCPT ); Sun, 24 Jan 2016 14:25:02 -0500 Received: from unicorn.mansr.com ([81.2.72.234]:59259 "EHLO unicorn.mansr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753630AbcAXTY6 (ORCPT ); Sun, 24 Jan 2016 14:24:58 -0500 Received: by unicorn.mansr.com (Postfix, from userid 51770) id 2C39115632; Sun, 24 Jan 2016 19:24:57 +0000 (GMT) From: Mans Rullgard To: Viresh Kumar , Andy Shevchenko , Vinod Koul , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: Dan Williams Subject: [PATCH 05/15] dmaengine: dw: set LMS field in descriptors Date: Sun, 24 Jan 2016 19:21:52 +0000 Message-Id: <1453663322-14474-6-git-send-email-mans@mansr.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1453663322-14474-1-git-send-email-mans@mansr.com> References: <1453663322-14474-1-git-send-email-mans@mansr.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The LMS field indicates from which master the descriptor is to be read. This patch assumes this is always the same as the memory side in a peripheral transfer which is true for all known systems. Signed-off-by: Mans Rullgard Signed-off-by: Andy Shevchenko --- drivers/dma/dw/core.c | 19 +++++++++---------- drivers/dma/dw/regs.h | 4 ++++ 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 1e29efad2bf1..bbae43451529 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -265,7 +265,7 @@ static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) dwc_initialize(dwc); - channel_writel(dwc, LLP, first->txd.phys); + channel_writel(dwc, LLP, first->txd.phys | DWC_LLP_LMS(dwc->m_master)); channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); channel_writel(dwc, CTL_HI, 0); @@ -431,7 +431,7 @@ static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) dwc->residue = desc->total_len; /* Check first descriptors addr */ - if (desc->txd.phys == llp) { + if (desc->txd.phys == DWC_LLP_LOC(llp)) { spin_unlock_irqrestore(&dwc->lock, flags); return; } @@ -756,7 +756,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, if (!first) { first = desc; } else { - lli_write(prev, llp, desc->txd.phys); + lli_write(prev, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master)); list_add_tail(&desc->desc_node, &first->tx_list); } prev = desc; @@ -853,7 +853,7 @@ slave_sg_todev_fill_desc: if (!first) { first = desc; } else { - lli_write(prev, llp, desc->txd.phys); + lli_write(prev, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master)); list_add_tail(&desc->desc_node, &first->tx_list); } prev = desc; @@ -908,7 +908,7 @@ slave_sg_fromdev_fill_desc: if (!first) { first = desc; } else { - lli_write(prev, llp, desc->txd.phys); + lli_write(prev, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master)); list_add_tail(&desc->desc_node, &first->tx_list); } prev = desc; @@ -1427,13 +1427,13 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, cdesc->desc[i] = desc; if (last) - lli_write(last, llp, desc->txd.phys); + lli_write(last, llp, desc->txd.phys | DWC_LLP_LMS(dwc->m_master)); last = desc; } /* Let's make a cyclic list */ - lli_write(last, llp, cdesc->desc[0]->txd.phys); + lli_write(last, llp, cdesc->desc[0]->txd.phys | DWC_LLP_LMS(dwc->m_master)); dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf %pad len %zu period %zu periods %d\n", @@ -1635,9 +1635,8 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) dwc->block_size = pdata->block_size; /* Check if channel supports multi block transfer */ - channel_writel(dwc, LLP, 0xfffffffc); - dwc->nollp = - (channel_readl(dwc, LLP) & 0xfffffffc) == 0; + channel_writel(dwc, LLP, 0xffffffff); + dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0; channel_writel(dwc, LLP, 0); } } diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h index 0391f8ff6919..4e6ec2d75863 100644 --- a/drivers/dma/dw/regs.h +++ b/drivers/dma/dw/regs.h @@ -143,6 +143,10 @@ enum dw_dma_msize { DW_DMA_MSIZE_256, }; +/* Bitfields in LLP */ +#define DWC_LLP_LMS(x) ((x) & 3) /* list master select */ +#define DWC_LLP_LOC(x) ((x) & ~3) /* next lli */ + /* Bitfields in CTL_LO */ #define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ #define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */