From patchwork Mon Feb 22 16:03:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 8379331 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 80B3B9F2F0 for ; Mon, 22 Feb 2016 16:05:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6446A20513 for ; Mon, 22 Feb 2016 16:05:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 13CDF20443 for ; Mon, 22 Feb 2016 16:05:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754878AbcBVQFE (ORCPT ); Mon, 22 Feb 2016 11:05:04 -0500 Received: from mga03.intel.com ([134.134.136.65]:50929 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751959AbcBVQFA (ORCPT ); Mon, 22 Feb 2016 11:05:00 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 22 Feb 2016 08:04:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,485,1449561600"; d="scan'208";a="908684202" Received: from black.fi.intel.com ([10.237.72.93]) by fmsmga001.fm.intel.com with ESMTP; 22 Feb 2016 08:03:58 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id E37DE4A3; Mon, 22 Feb 2016 18:03:51 +0200 (EET) From: Andy Shevchenko To: Viresh Kumar , Andy Shevchenko , Vinod Koul , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Rob Herring , Hans-Christian Egtvedt , Tejun Heo , Mark Brown , Greg Kroah-Hartman , Mark Rutland , Vineet Gupta Cc: Mans Rullgard Subject: [PATCH v2 07/15] dmaengine: dw: revisit data_width property Date: Mon, 22 Feb 2016 18:03:42 +0200 Message-Id: <1456157030-54677-8-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1456157030-54677-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1456157030-54677-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are several changes are done here: - Convert the property to be in bytes Much more convenient than keeping encoded value. - Use one value for all AHB masters for now It seems in practice we have no controllers where masters have different data bus width, we still might return to distinct values when there is a use case. - Rename data_width to data-width in the device tree bindings. - While here, replace dwc_fast_ffs() by __ffs(). Signed-off-by: Andy Shevchenko Signed-off-by: Mans Rullgard --- Documentation/devicetree/bindings/dma/snps-dma.txt | 5 ++- arch/arc/boot/dts/abilis_tb10x.dtsi | 2 +- arch/arm/boot/dts/spear13xx.dtsi | 4 +-- drivers/dma/dw/core.c | 40 +++------------------- drivers/dma/dw/platform.c | 10 +++--- drivers/dma/dw/regs.h | 2 +- include/linux/platform_data/dma-dw.h | 5 ++- 7 files changed, 18 insertions(+), 50 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt index c99c1ff..eb48229 100644 --- a/Documentation/devicetree/bindings/dma/snps-dma.txt +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt @@ -13,8 +13,7 @@ Required properties: - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1: increase from chan n->0 - block_size: Maximum block size supported by the controller -- data_width: Maximum data width supported by hardware per AHB master - (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) +- data-width: Maximum data width supported by hardware (in bytes, power of 2) Optional properties: @@ -38,7 +37,7 @@ Example: chan_allocation_order = <1>; chan_priority = <1>; block_size = <0xfff>; - data_width = <3 3>; + data-width = <8>; }; DMA clients connected to the Designware DMA controller must use the format diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi index cfb5052..2f53bed 100644 --- a/arch/arc/boot/dts/abilis_tb10x.dtsi +++ b/arch/arc/boot/dts/abilis_tb10x.dtsi @@ -112,7 +112,7 @@ chan_allocation_order = <0>; chan_priority = <1>; block_size = <0x7ff>; - data_width = <2>; + data-width = <4>; clocks = <&ahb_clk>; clock-names = "hclk"; }; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 14594ce..474b66f 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -117,7 +117,7 @@ chan_priority = <1>; block_size = <0xfff>; dma-masters = <2>; - data_width = <3 3>; + data-width = <8>; }; dma@eb000000 { @@ -133,7 +133,7 @@ chan_allocation_order = <1>; chan_priority = <1>; block_size = <0xfff>; - data_width = <3 3>; + data-width = <8>; }; fsmc: flash@b0000000 { diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index d53e997..85b65e6 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -167,21 +167,6 @@ static void dwc_initialize(struct dw_dma_chan *dwc) /*----------------------------------------------------------------------*/ -static inline unsigned int dwc_fast_ffs(unsigned long long v) -{ - /* - * We can be a lot more clever here, but this should take care - * of the most common optimization. - */ - if (!(v & 7)) - return 3; - else if (!(v & 3)) - return 2; - else if (!(v & 1)) - return 1; - return 0; -} - static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) { dev_err(chan2dev(&dwc->chan), @@ -711,7 +696,6 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t offset; unsigned int src_width; unsigned int dst_width; - unsigned int data_width; u32 ctllo; dev_vdbg(chan2dev(chan), @@ -725,10 +709,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, dwc->direction = DMA_MEM_TO_MEM; - data_width = dw->data_width[dwc->m_master]; - - src_width = dst_width = min_t(unsigned int, data_width, - dwc_fast_ffs(src | dest | len)); + src_width = dst_width = __ffs(dw->data_width | src | dest | len); ctllo = DWC_DEFAULT_CTLLO(chan) | DWC_CTLL_DST_WIDTH(dst_width) @@ -791,7 +772,6 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, dma_addr_t reg; unsigned int reg_width; unsigned int mem_width; - unsigned int data_width; unsigned int i; struct scatterlist *sg; size_t total_len = 0; @@ -817,8 +797,6 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : DWC_CTLL_FC(DW_DMA_FC_D_M2P); - data_width = dw->data_width[dwc->m_master]; - for_each_sg(sgl, sg, sg_len, i) { struct dw_desc *desc; u32 len, dlen, mem; @@ -826,8 +804,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, mem = sg_dma_address(sg); len = sg_dma_len(sg); - mem_width = min_t(unsigned int, - data_width, dwc_fast_ffs(mem | len)); + mem_width = __ffs(dw->data_width | mem | len); slave_sg_todev_fill_desc: desc = dwc_desc_get(dwc); @@ -873,8 +850,6 @@ slave_sg_todev_fill_desc: ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : DWC_CTLL_FC(DW_DMA_FC_D_P2M); - data_width = dw->data_width[dwc->m_master]; - for_each_sg(sgl, sg, sg_len, i) { struct dw_desc *desc; u32 len, dlen, mem; @@ -882,8 +857,7 @@ slave_sg_todev_fill_desc: mem = sg_dma_address(sg); len = sg_dma_len(sg); - mem_width = min_t(unsigned int, - data_width, dwc_fast_ffs(mem | len)); + mem_width = __ffs(dw->data_width | mem | len); slave_sg_fromdev_fill_desc: desc = dwc_desc_get(dwc); @@ -1536,10 +1510,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) /* Get hardware configuration parameters */ pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; - for (i = 0; i < pdata->nr_masters; i++) { - pdata->data_width[i] = - (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; - } + pdata->data_width = 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(0) & 3); max_blk_size = dma_readl(dw, MAX_BLK_SIZE); /* Fill platform data with the default values */ @@ -1561,8 +1532,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) /* Get hardware configuration parameters */ dw->nr_masters = pdata->nr_masters; - for (i = 0; i < dw->nr_masters; i++) - dw->data_width[i] = pdata->data_width[i]; + dw->data_width = pdata->data_width; /* Calculate all channel mask before DMA setup */ dw->all_chan_mask = (1 << pdata->nr_channels) - 1; diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c index d3e1abc..0106bc5 100644 --- a/drivers/dma/dw/platform.c +++ b/drivers/dma/dw/platform.c @@ -102,8 +102,8 @@ dw_dma_parse_dt(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct dw_dma_platform_data *pdata; - u32 tmp, arr[DW_DMA_MAX_NR_MASTERS]; u32 nr_channels; + u32 tmp; if (!np) { dev_err(&pdev->dev, "Missing DT data\n"); @@ -138,10 +138,10 @@ dw_dma_parse_dt(struct platform_device *pdev) pdata->nr_masters = tmp; } - if (!of_property_read_u32_array(np, "data_width", arr, - pdata->nr_masters)) - for (tmp = 0; tmp < pdata->nr_masters; tmp++) - pdata->data_width[tmp] = arr[tmp]; + if (!of_property_read_u32(np, "data-width", &tmp)) + pdata->data_width = tmp; + else if (!of_property_read_u32(np, "data_width", &tmp)) + pdata->data_width = BIT(tmp); return pdata; } diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h index feb3a4a..d0f9173 100644 --- a/drivers/dma/dw/regs.h +++ b/drivers/dma/dw/regs.h @@ -285,7 +285,7 @@ struct dw_dma { /* hardware configuration */ unsigned char nr_masters; - unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; + unsigned char data_width; }; static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index b881b97..4120a3e 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h @@ -42,8 +42,7 @@ struct dw_dma_slave { * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. * @block_size: Maximum block size supported by the controller * @nr_masters: Number of AHB masters supported by the controller - * @data_width: Maximum data width supported by hardware per AHB master - * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) + * @data_width: Maximum data width supported by hardware (in bytes) */ struct dw_dma_platform_data { unsigned int nr_channels; @@ -57,7 +56,7 @@ struct dw_dma_platform_data { unsigned char chan_priority; unsigned short block_size; unsigned char nr_masters; - unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; + unsigned char data_width; }; #endif /* _PLATFORM_DATA_DMA_DW_H */