From patchwork Sat Mar 5 10:52:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Sperl X-Patchwork-Id: 8509891 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 26BFD9F659 for ; Sat, 5 Mar 2016 10:52:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 282292022A for ; Sat, 5 Mar 2016 10:52:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AE01C2026F for ; Sat, 5 Mar 2016 10:52:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760668AbcCEKwy (ORCPT ); Sat, 5 Mar 2016 05:52:54 -0500 Received: from 212-186-180-163.dynamic.surfer.at ([212.186.180.163]:46196 "EHLO cgate.sperl.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760672AbcCEKwx (ORCPT ); Sat, 5 Mar 2016 05:52:53 -0500 Received: from rasp3a.intern.sperl.org (account martin@sperl.org [10.10.10.43] verified) by sperl.org (CommuniGate Pro SMTP 6.1.2) with ESMTPSA id 6405653; Sat, 05 Mar 2016 10:52:36 +0000 From: kernel@martin.sperl.org To: Rob Herring , Stephen Warren , Lee Jones , Eric Anholt , Vinod Koul , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org Cc: Martin Sperl Subject: [PATCH v3 08/11] dmaengine: bcm2835: limit max length based on channel type Date: Sat, 5 Mar 2016 10:52:19 +0000 Message-Id: <1457175142-28665-9-git-send-email-kernel@martin.sperl.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1457175142-28665-1-git-send-email-kernel@martin.sperl.org> References: <1457175142-28665-1-git-send-email-kernel@martin.sperl.org> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Martin Sperl The bcm2835 dma system has 2 basic types of dma-channels: * "normal" channels * "light" channels Lite channels are limited in several aspects: * internal data-structure is 128 bit (not 256) * does not support BCM2835_DMA_TDMODE (2D) * DMA length register is limited to 16 bit. so 0-65535 (not 0-65536 as mentioned in the official datasheet) * BCM2835_DMA_S/D_IGNORE are not supported The detection of the type of mode is implemented by looking at the LITE bit in the DEBUG register for each channel. This allows automatic detection. Based on this the maximum block size is set to (64K - 4) or to 1G and this limit is honored during generation of control block chains. The effect is that when a LITE channel is used more control blocks are used to do the same transfer (compared to a normal channel). As there are several sources/target DREQS that are 32 bit wide we need to have the transfer to be a multiple of 4 as this would break he transfer otherwise. This is why the limit of (64K - 4) was chosen over the alternative of (64K - 4K). Signed-off-by: Martin Sperl --- drivers/dma/bcm2835-dma.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c index 1ae53b8..024c949 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c @@ -83,6 +83,8 @@ struct bcm2835_chan { int irq_number; unsigned long irq_flags; + + bool is_lite_channel; }; struct bcm2835_desc { @@ -185,6 +187,16 @@ struct bcm2835_desc { #define BCM2835_DMA_IRQ_SHARED_DEFAULT 11 #define BCM2835_DMA_IRQ_ALL_DEFAULT 12 +/* the max dma length for different channels */ +#define MAX_DMA_LEN SZ_1G +#define MAX_LITE_DMA_LEN (SZ_64K - 4) + +static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c) +{ + /* lite and normal channels have different max frame length */ + return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN; +} + /* how many frames of max_len size do we need to transfer len bytes */ static inline size_t bcm2835_dma_frames_for_length(size_t len, size_t max_len) @@ -233,8 +245,10 @@ static void bcm2835_dma_create_cb_set_length( size_t *total_len, u32 finalextrainfo) { - /* set the length */ - control_block->length = len; + size_t max_len = bcm2835_dma_max_frame_length(chan); + + /* set the length taking lite-channel limitations into account */ + control_block->length = min_t(u32, len, max_len); /* finished if we have no period_length */ if (!period_len) @@ -570,6 +584,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( dma_addr_t src, dst; u32 info = BCM2835_DMA_WAIT_RESP; u32 extra = BCM2835_DMA_INT_EN; + size_t max_len = bcm2835_dma_max_frame_length(c); size_t frames; /* Grab configuration */ @@ -612,7 +627,10 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( } /* calculate number of frames */ - frames = DIV_ROUND_UP(buf_len, period_len); + frames = /* number of periods */ + DIV_ROUND_UP(buf_len, period_len) * + /* number of frames per period */ + bcm2835_dma_frames_for_length(period_len, max_len); /* * allocate the CB chain @@ -713,6 +731,11 @@ static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, c->irq_number = irq; c->irq_flags = irq_flags; + /* check in DEBUG register if this is a LITE channel */ + if (readl(c->chan_base + BCM2835_DMA_DEBUG) & + BCM2835_DMA_DEBUG_LITE) + c->is_lite_channel = true; + return 0; }