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[v1,4/6] dmaengine: hsu: allow more than 3 descriptors

Message ID 1458303996-126698-5-git-send-email-andriy.shevchenko@linux.intel.com (mailing list archive)
State Accepted
Headers show

Commit Message

Andy Shevchenko March 18, 2016, 12:26 p.m. UTC
Current code allows only up to 3 descriptors to be programmed to the hardware
since it is used wrong calculations. Change % to min_t() to allow as many
descriptors as user supplied. At once it could be programmed up to 4
descriptors due to hardware limitations.

The issue was found under stress test, so it might not bother ordinary users.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/dma/hsu/hsu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/drivers/dma/hsu/hsu.c b/drivers/dma/hsu/hsu.c
index ee51051..da1b399 100644
--- a/drivers/dma/hsu/hsu.c
+++ b/drivers/dma/hsu/hsu.c
@@ -77,8 +77,8 @@  static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
 	hsu_chan_writel(hsuc, HSU_CH_MTSR, mtsr);
 
 	/* Set descriptors */
-	count = (desc->nents - desc->active) % HSU_DMA_CHAN_NR_DESC;
-	for (i = 0; i < count; i++) {
+	count = desc->nents - desc->active;
+	for (i = 0; i < count && i < HSU_DMA_CHAN_NR_DESC; i++) {
 		hsu_chan_writel(hsuc, HSU_CH_DxSAR(i), desc->sg[i].addr);
 		hsu_chan_writel(hsuc, HSU_CH_DxTSR(i), desc->sg[i].len);