From patchwork Fri May 6 15:17:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 9033961 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6E84C9F30C for ; Fri, 6 May 2016 15:19:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 77D7C2039D for ; Fri, 6 May 2016 15:19:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8CB4C20390 for ; Fri, 6 May 2016 15:19:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758599AbcEFPSV (ORCPT ); Fri, 6 May 2016 11:18:21 -0400 Received: from mga03.intel.com ([134.134.136.65]:26741 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758367AbcEFPRa (ORCPT ); Fri, 6 May 2016 11:17:30 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP; 06 May 2016 08:17:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,587,1455004800"; d="scan'208";a="697862005" Received: from black.fi.intel.com ([10.237.72.93]) by FMSMGA003.fm.intel.com with ESMTP; 06 May 2016 08:17:27 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id AAFCD896; Fri, 6 May 2016 18:17:21 +0300 (EEST) From: Andy Shevchenko To: Bryan O'Donoghue , Peter Hurley , linux-serial@vger.kernel.org, Vinod Koul , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Greg Kroah-Hartman , ismo.puustinen@intel.com, Heikki Krogerus Cc: Andy Shevchenko Subject: [PATCH v5 11/11] serial: 8250_lpss: enable DMA on Intel Quark UART Date: Fri, 6 May 2016 18:17:20 +0300 Message-Id: <1462547840-14091-12-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462547840-14091-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1462547840-14091-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DMA on Intel Quark SoC is a part of UART IP block. Enable it. Signed-off-by: Andy Shevchenko --- drivers/tty/serial/8250/8250_lpss.c | 61 +++++++++++++++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/8250/8250_lpss.c b/drivers/tty/serial/8250/8250_lpss.c index c83fd51..0f4134a 100644 --- a/drivers/tty/serial/8250/8250_lpss.c +++ b/drivers/tty/serial/8250/8250_lpss.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include "8250.h" @@ -47,6 +47,7 @@ struct lpss8250_board { unsigned long freq; unsigned int base_baud; int (*setup)(struct lpss8250 *, struct uart_port *p); + void (*exit)(struct lpss8250 *); }; struct lpss8250 { @@ -55,6 +56,7 @@ struct lpss8250 { /* DMA parameters */ struct uart_8250_dma dma; + struct dw_dma_chip dma_chip; struct dw_dma_slave dma_param; u8 dma_maxburst; }; @@ -150,17 +152,61 @@ static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port) return 0; } +static const struct dw_dma_platform_data qrk_serial_dma_pdata = { + .nr_channels = 2, + .is_private = true, + .is_nollp = true, + .chan_allocation_order = CHAN_ALLOCATION_ASCENDING, + .chan_priority = CHAN_PRIORITY_ASCENDING, + .block_size = 4095, + .nr_masters = 1, + .data_width = {4}, +}; + static int qrk_serial_setup(struct lpss8250 *lpss, struct uart_port *port) { + struct uart_8250_dma *dma = &lpss->dma; + struct dw_dma_chip *chip = &lpss->dma_chip; + struct dw_dma_slave *param = &lpss->dma_param; struct pci_dev *pdev = to_pci_dev(port->dev); + int ret; pci_enable_msi(pdev); port->irq = pdev->irq; + chip->dev = &pdev->dev; + chip->irq = pdev->irq; + chip->regs = pci_ioremap_bar(pdev, 1); + chip->pdata = &qrk_serial_dma_pdata; + + /* Falling back to PIO mode if DMA probing fails */ + ret = dw_dma_probe(chip); + if (ret) + return 0; + + /* Special DMA address for UART */ + dma->rx_dma_addr = 0xfffff000; + dma->tx_dma_addr = 0xfffff000; + + param->dma_dev = &pdev->dev; + param->src_id = 0; + param->dst_id = 1; + param->hs_polarity = true; + + lpss->dma_maxburst = 8; return 0; } +static void qrk_serial_exit(struct lpss8250 *lpss) +{ + struct dw_dma_slave *param = &lpss->dma_param; + + if (!param->dma_dev) + return; + dw_dma_remove(&lpss->dma_chip); +} + static bool lpss8250_dma_filter(struct dma_chan *chan, void *param) { struct dw_dma_slave *dws = param; @@ -243,22 +289,30 @@ static int lpss8250_probe(struct pci_dev *pdev, const struct pci_device_id *id) ret = lpss8250_dma_setup(lpss, &uart); if (ret) - return ret; + goto err_exit; ret = serial8250_register_8250_port(&uart); if (ret < 0) - return ret; + goto err_exit; lpss->line = ret; pci_set_drvdata(pdev, lpss); return 0; + +err_exit: + if (lpss->board->exit) + lpss->board->exit(lpss); + return ret; } static void lpss8250_remove(struct pci_dev *pdev) { struct lpss8250 *lpss = pci_get_drvdata(pdev); + if (lpss->board->exit) + lpss->board->exit(lpss); + serial8250_unregister_port(lpss->line); } @@ -272,6 +326,7 @@ static const struct lpss8250_board qrk_board = { .freq = 44236800, .base_baud = 2764800, .setup = qrk_serial_setup, + .exit = qrk_serial_exit, }; #define LPSS_DEVICE(id, board) { PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&board }