From patchwork Fri May 6 15:17:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 9033951 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8AEACBF29F for ; Fri, 6 May 2016 15:18:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AFA7E201BC for ; Fri, 6 May 2016 15:18:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 29F8220398 for ; Fri, 6 May 2016 15:18:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758617AbcEFPSW (ORCPT ); Fri, 6 May 2016 11:18:22 -0400 Received: from mga03.intel.com ([134.134.136.65]:58921 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758343AbcEFPRa (ORCPT ); Fri, 6 May 2016 11:17:30 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP; 06 May 2016 08:17:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,587,1455004800"; d="scan'208";a="697862002" Received: from black.fi.intel.com ([10.237.72.93]) by FMSMGA003.fm.intel.com with ESMTP; 06 May 2016 08:17:27 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 80DD3207; Fri, 6 May 2016 18:17:21 +0300 (EEST) From: Andy Shevchenko To: Bryan O'Donoghue , Peter Hurley , linux-serial@vger.kernel.org, Vinod Koul , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Greg Kroah-Hartman , ismo.puustinen@intel.com, Heikki Krogerus Cc: Andy Shevchenko Subject: [PATCH v5 07/11] serial: 8250: enable AFE on ports where FIFO is 16 bytes Date: Fri, 6 May 2016 18:17:16 +0300 Message-Id: <1462547840-14091-8-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462547840-14091-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1462547840-14091-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Intel Quark has 16550A compatible UART with autoflow feature enabled. It has only 16 bytes of FIFO. Currently serial8250_do_set_termios() prevents to enable autoflow since the minimum requirement of 32 bytes of FIFO size. Drop a FIFO size limitation to allow autoflow control be enabled on such UARTs. While here, comment out UART_CAP_AFE for PORT_AR7 since it wasn't working and it will be not a good idea to use it in conjunction with trigger level of 1 byte. Suggested-by: Peter Hurley Reviewed-by: Peter Hurley Signed-off-by: Andy Shevchenko --- drivers/tty/serial/8250/8250_port.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index d403603..be9cc37 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -178,7 +178,7 @@ static const struct serial8250_config uart_config[] = { .fifo_size = 16, .tx_loadsz = 16, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, - .flags = UART_CAP_FIFO | UART_CAP_AFE, + .flags = UART_CAP_FIFO /* | UART_CAP_AFE */, }, [PORT_U6_16550A] = { .name = "U6_16550A", @@ -2550,12 +2550,9 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, /* * MCR-based auto flow control. When AFE is enabled, RTS will be * deasserted when the receive FIFO contains more characters than - * the trigger, or the MCR RTS bit is cleared. In the case where - * the remote UART is not using CTS auto flow control, we must - * have sufficient FIFO entries for the latency of the remote - * UART to respond. IOW, at least 32 bytes of FIFO. + * the trigger, or the MCR RTS bit is cleared. */ - if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) { + if (up->capabilities & UART_CAP_AFE) { up->mcr &= ~UART_MCR_AFE; if (termios->c_cflag & CRTSCTS) up->mcr |= UART_MCR_AFE;