From patchwork Mon May 16 08:37:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Jiada" X-Patchwork-Id: 9099031 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E6CEE9F1D3 for ; Mon, 16 May 2016 08:38:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2325E20274 for ; Mon, 16 May 2016 08:38:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 18EEB202B8 for ; Mon, 16 May 2016 08:38:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753734AbcEPIiN (ORCPT ); Mon, 16 May 2016 04:38:13 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:33329 "EHLO relay1.mentorg.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753618AbcEPIiL (ORCPT ); Mon, 16 May 2016 04:38:11 -0400 Received: from svr-orw-fem-04.mgc.mentorg.com ([147.34.97.41]) by relay1.mentorg.com with esmtp id 1b2E2U-00023u-Iu from Jiada_Wang@mentor.com ; Mon, 16 May 2016 01:38:10 -0700 Received: from jiwang-OptiPlex-980.tokyo.mentorg.com (147.34.91.1) by svr-orw-fem-04.mgc.mentorg.com (147.34.97.41) with Microsoft SMTP Server id 14.3.224.2; Mon, 16 May 2016 01:38:10 -0700 From: Jiada Wang To: , CC: , , , Subject: [PATCH 10/10] dma: imx-sdma: clear channel0 interrupt bit in irq routine Date: Mon, 16 May 2016 17:37:58 +0900 Message-ID: <1463387878-7643-11-git-send-email-jiada_wang@mentor.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1463387878-7643-1-git-send-email-jiada_wang@mentor.com> References: <1463387878-7643-1-git-send-email-jiada_wang@mentor.com> MIME-Version: 1.0 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When SDMA channel0 timeouts, even it's disabled in error path, but sometimes we still see its interrupt bit be asserted, which causes irq routine be triggered continuously because no one else clears this bit. This commit clears channel0 interrupt as well in irq routine, so that even channel0 timeouts, it won't cause irq storm, also adds lock to prevent irq routine to clear this bit when sdma_run_channel0() is busy checking it. Signed-off-by: Jiada Wang --- drivers/dma/imx-sdma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 8b20bf4..ca1c984 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -768,12 +768,16 @@ static void sdma_tasklet(unsigned long data) static irqreturn_t sdma_int_handler(int irq, void *dev_id) { struct sdma_engine *sdma = dev_id; - unsigned long stat; + unsigned long stat, flags; + + spin_lock_irqsave(&sdma->channel_0_lock, flags); stat = readl_relaxed(sdma->regs + SDMA_H_INTR); + writel_relaxed(stat, sdma->regs + SDMA_H_INTR); /* not interested in channel 0 interrupts */ stat &= ~1; - writel_relaxed(stat, sdma->regs + SDMA_H_INTR); + + spin_unlock_irqrestore(&sdma->channel_0_lock, flags); while (stat) { int channel = fls(stat) - 1;