From patchwork Tue May 17 03:48:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Jiada" X-Patchwork-Id: 9108541 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EF503BF29F for ; Tue, 17 May 2016 03:49:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 17536201B9 for ; Tue, 17 May 2016 03:49:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3C55520120 for ; Tue, 17 May 2016 03:49:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755022AbcEQDtP (ORCPT ); Mon, 16 May 2016 23:49:15 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:38271 "EHLO relay1.mentorg.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754924AbcEQDtN (ORCPT ); Mon, 16 May 2016 23:49:13 -0400 Received: from svr-orw-fem-05.mgc.mentorg.com ([147.34.97.43]) by relay1.mentorg.com with esmtp id 1b2W0O-0004zx-JY from Jiada_Wang@mentor.com ; Mon, 16 May 2016 20:49:12 -0700 Received: from jiwang-OptiPlex-980.tokyo.mentorg.com (147.34.91.1) by svr-orw-fem-05.mgc.mentorg.com (147.34.97.43) with Microsoft SMTP Server id 14.3.224.2; Mon, 16 May 2016 20:49:12 -0700 From: Jiada Wang To: , CC: , , , , , Subject: [PATCH 10/10] dma: imx-sdma: clear channel0 interrupt bit in irq routine Date: Tue, 17 May 2016 12:48:56 +0900 Message-ID: <1463456936-10634-11-git-send-email-jiada_wang@mentor.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1463456936-10634-1-git-send-email-jiada_wang@mentor.com> References: <1463456936-10634-1-git-send-email-jiada_wang@mentor.com> MIME-Version: 1.0 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When SDMA channel0 timeouts, even it's disabled in error path, but sometimes we still see its interrupt bit be asserted, which causes irq routine be triggered continuously because no one else clears this bit. This commit clears channel0 interrupt as well in irq routine, so that even channel0 timeouts, it won't cause irq storm, also adds lock to prevent irq routine to clear this bit when sdma_run_channel0() is busy checking it. Signed-off-by: Jiada Wang --- drivers/dma/imx-sdma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 8b20bf4..ca1c984 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -768,12 +768,16 @@ static void sdma_tasklet(unsigned long data) static irqreturn_t sdma_int_handler(int irq, void *dev_id) { struct sdma_engine *sdma = dev_id; - unsigned long stat; + unsigned long stat, flags; + + spin_lock_irqsave(&sdma->channel_0_lock, flags); stat = readl_relaxed(sdma->regs + SDMA_H_INTR); + writel_relaxed(stat, sdma->regs + SDMA_H_INTR); /* not interested in channel 0 interrupts */ stat &= ~1; - writel_relaxed(stat, sdma->regs + SDMA_H_INTR); + + spin_unlock_irqrestore(&sdma->channel_0_lock, flags); while (stat) { int channel = fls(stat) - 1;