From patchwork Mon Jun 20 09:17:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 9186973 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C7DB8607D1 for ; Mon, 20 Jun 2016 09:26:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B1BCC24B5B for ; Mon, 20 Jun 2016 09:26:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A649726490; Mon, 20 Jun 2016 09:26:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D01324B5B for ; Mon, 20 Jun 2016 09:26:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752526AbcFTJSw (ORCPT ); Mon, 20 Jun 2016 05:18:52 -0400 Received: from mga01.intel.com ([192.55.52.88]:20367 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751927AbcFTJSI (ORCPT ); Mon, 20 Jun 2016 05:18:08 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 20 Jun 2016 02:18:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,497,1459839600"; d="scan'208";a="1005748939" Received: from black.fi.intel.com ([10.237.72.93]) by fmsmga002.fm.intel.com with ESMTP; 20 Jun 2016 02:18:04 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id A801C182; Mon, 20 Jun 2016 12:18:03 +0300 (EEST) From: Andy Shevchenko To: Bryan O'Donoghue , Peter Hurley , linux-serial@vger.kernel.org, Vinod Koul , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Greg Kroah-Hartman , ismo.puustinen@intel.com, Heikki Krogerus Cc: Andy Shevchenko Subject: [PATCH v9 04/11] dmaengine: dw: override LLP support if asked in platform data Date: Mon, 20 Jun 2016 12:17:55 +0300 Message-Id: <1466414282-96691-5-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1466414282-96691-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1466414282-96691-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is at least one known device, i.e. UART on Intel Galileo, that works unreliably in case multi block transfer support in DMA mode is in use. Override autodetection by user provided data. Acked-by: Vinod Koul Signed-off-by: Andy Shevchenko --- drivers/dma/dw/core.c | 10 +++++++--- include/linux/platform_data/dma-dw.h | 2 ++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 59f571c..d2d1d51 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -1573,9 +1573,13 @@ int dw_dma_probe(struct dw_dma_chip *chip) dwc->block_size = pdata->block_size; /* Check if channel supports multi block transfer */ - channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff)); - dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0; - channel_writel(dwc, LLP, 0); + if (pdata->is_nollp) { + dwc->nollp = pdata->is_nollp; + } else { + channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff)); + dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0; + channel_writel(dwc, LLP, 0); + } } } diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index 4636c93..5f0e11e 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h @@ -40,6 +40,7 @@ struct dw_dma_slave { * @is_private: The device channels should be marked as private and not for * by the general purpose DMA channel allocator. * @is_memcpy: The device channels do support memory-to-memory transfers. + * @is_nollp: The device channels does not support multi block transfers. * @chan_allocation_order: Allocate channels starting from 0 or 7 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. * @block_size: Maximum block size supported by the controller @@ -51,6 +52,7 @@ struct dw_dma_platform_data { unsigned int nr_channels; bool is_private; bool is_memcpy; + bool is_nollp; #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ unsigned char chan_allocation_order;