From patchwork Wed Nov 16 13:56:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 9431637 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1F5446047D for ; Wed, 16 Nov 2016 13:57:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0DA3928F00 for ; Wed, 16 Nov 2016 13:57:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0216F28EC1; Wed, 16 Nov 2016 13:57:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A406228EC1 for ; Wed, 16 Nov 2016 13:57:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932727AbcKPN5S (ORCPT ); Wed, 16 Nov 2016 08:57:18 -0500 Received: from smtprelay.synopsys.com ([198.182.60.111]:46030 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932201AbcKPN5R (ORCPT ); Wed, 16 Nov 2016 08:57:17 -0500 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id 5007910C144B; Wed, 16 Nov 2016 05:57:16 -0800 (PST) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 3129CB9F; Wed, 16 Nov 2016 05:57:16 -0800 (PST) Received: from paltsev-8460-lab.internal.synopsys.com (paltsev-8460-lab.internal.synopsys.com [10.121.14.113]) by mailhost.synopsys.com (Postfix) with ESMTP id AB206B8B; Wed, 16 Nov 2016 05:57:13 -0800 (PST) From: Eugeniy Paltsev To: devicetree@vger.kernel.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, andriy.shevchenko@linux.intel.com, vireshk@kernel.org, dan.j.williams@intel.com, vinod.koul@intel.com, dmaengine@vger.kernel.org, linux-snps-arc@lists.infradead.org, Eugeniy Paltsev Subject: [PATCH 3/4] DW DMAC: add hw-llp property to device tree Date: Wed, 16 Nov 2016 16:56:54 +0300 Message-Id: <1479304615-11360-4-git-send-email-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1479304615-11360-1-git-send-email-Eugeniy.Paltsev@synopsys.com> References: <1479304615-11360-1-git-send-email-Eugeniy.Paltsev@synopsys.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Several versions of DW DMAC have multi block transfers hardware support. Hardware support of multi block transfers is disabled by default if we use DT to configure DMAC and software emulation of multi block transfers used instead. Add hw-llp property, so it is possible to enable hardware multi block transfers (if present) via DT. Signed-off-by: Eugeniy Paltsev --- drivers/dma/dw/core.c | 2 +- drivers/dma/dw/platform.c | 5 +++++ include/linux/platform_data/dma-dw.h | 4 ++-- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index c2c0a61..e3ff4ea 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip) (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; } else { dwc->block_size = pdata->block_size; - dwc->nollp = pdata->is_nollp; + dwc->nollp = pdata->hw_llp[i]; } } diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c index daeceac..2722e60 100644 --- a/drivers/dma/dw/platform.c +++ b/drivers/dma/dw/platform.c @@ -151,6 +151,11 @@ dw_dma_parse_dt(struct platform_device *pdev) pdata->data_width[tmp] = BIT(arr[tmp] & 0x07); } + if (!of_property_read_u32_array(np, "hw-llp", arr, nr_masters)) { + for (tmp = 0; tmp < nr_masters; tmp++) + pdata->hw_llp[tmp] = arr[tmp]; + } + return pdata; } #else diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index 5f0e11e..5bc8124 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h @@ -40,19 +40,18 @@ struct dw_dma_slave { * @is_private: The device channels should be marked as private and not for * by the general purpose DMA channel allocator. * @is_memcpy: The device channels do support memory-to-memory transfers. - * @is_nollp: The device channels does not support multi block transfers. * @chan_allocation_order: Allocate channels starting from 0 or 7 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. * @block_size: Maximum block size supported by the controller * @nr_masters: Number of AHB masters supported by the controller * @data_width: Maximum data width supported by hardware per AHB master * (in bytes, power of 2) + * @hw_llp: Multi block transfers supported by hardware per AHB master. */ struct dw_dma_platform_data { unsigned int nr_channels; bool is_private; bool is_memcpy; - bool is_nollp; #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ unsigned char chan_allocation_order; @@ -62,6 +61,7 @@ struct dw_dma_platform_data { unsigned int block_size; unsigned char nr_masters; unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; + unsigned char hw_llp[DW_DMA_MAX_NR_MASTERS]; }; #endif /* _PLATFORM_DATA_DMA_DW_H */