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([37.171.147.92]) by smtp.gmail.com with ESMTPSA id t103sm25283741wrc.43.2017.03.13.07.16.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 13 Mar 2017 07:16:15 -0700 (PDT) From: M'boumba Cedric Madianga To: vinod.koul@intel.com, robh+dt@kernel.org, mark.rutland@arm.com, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, dan.j.williams@intel.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: M'boumba Cedric Madianga Subject: [PATCH 1/5] dt-bindings: Document the STM32 DMAMUX bindings Date: Mon, 13 Mar 2017 15:15:57 +0100 Message-Id: <1489414561-28912-2-git-send-email-cedric.madianga@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489414561-28912-1-git-send-email-cedric.madianga@gmail.com> References: <1489414561-28912-1-git-send-email-cedric.madianga@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the documentation of device tree bindings for the STM32 DMAMUX. Signed-off-by: M'boumba Cedric Madianga --- .../devicetree/bindings/dma/stm32-dmamux.txt | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt new file mode 100644 index 0000000..1039420 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt @@ -0,0 +1,57 @@ +STM32 DMA MUX (DMA request router) + +Required properties: +- compatible: "st,stm32-dmamux" +- reg: Memory map for accessing module +- #dma-cells: Should be set to <4>. + For more details about the four cells, please see stm32-dma.txt + documentation binding file +- dma-masters: Phandle pointing to the DMA controller +- clocks: Input clock of the DMAMUX instance. + +Optional properties: +- dma-channels : Number of DMA channels supported. +- dma-requests : Number of DMA requests supported. +- resets: Reference to a reset controller asserting the DMA controller + +Example: + +/* DMA controller */ +dma2: dma-controller@40026400 { + compatible = "st,stm32-dma"; + reg = <0x40026400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&clk_hclk>; + #dma-cells = <4>; + st,mem2mem; + resets = <&rcc 150>; + st,dmamux; + dma-channels = <8>; +}; + +/* DMA mux */ +dmamux2: dma-router@40020820 { + compatible = "st,stm32-dmamux"; + reg = <0x40020800 0x1c>; + #dma-cells = <4>; + dma-requests = <128>; + dma-masters = <&dma2>; +}; + +/* DMA client */ +usart1: serial@40011000 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&clk_pclk2>; + dmas = <&dmamux2 0 41 0x400 0x00>, + <&dmamux2 1 42 0x400 0x00>; + dma-names = "rx", "tx"; +};