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Thu, 2 Jul 2020 06:54:16 +0000 From: Robin Gong To: vkoul@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, catalin.marinas@arm.com, will@kernel.org, dan.j.williams@intel.com, angelo@sysam.it Cc: kernel@pengutronix.de, linux-imx@nxp.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 8/9] arm64: dts: imx8qxp: add edma2 Date: Thu, 2 Jul 2020 23:08:08 +0800 Message-Id: <1593702489-21648-9-git-send-email-yibin.gong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593702489-21648-1-git-send-email-yibin.gong@nxp.com> References: <1593702489-21648-1-git-send-email-yibin.gong@nxp.com> X-ClientProxiedBy: SG2PR01CA0172.apcprd01.prod.exchangelabs.com (2603:1096:4:28::28) To VE1PR04MB6638.eurprd04.prod.outlook.com (2603:10a6:803:119::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from robin-OptiPlex-790.ap.freescale.net (119.31.174.67) by SG2PR01CA0172.apcprd01.prod.exchangelabs.com (2603:1096:4:28::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3153.24 via Frontend Transport; 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Signed-off-by: Robin Gong --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 38 ++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index e46faac..3f4fa59d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -300,6 +300,44 @@ status = "disabled"; }; + edma2: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */ + <0x5a290000 0x10000>, /* channel9 UART0 tx */ + <0x5a2a0000 0x10000>, /* channel10 UART1 rx */ + <0x5a2b0000 0x10000>, /* channel11 UART1 tx */ + <0x5a2c0000 0x10000>, /* channel12 UART2 rx */ + <0x5a2d0000 0x10000>, /* channel13 UART2 tx */ + <0x5a2e0000 0x10000>, /* channel14 UART3 rx */ + <0x5a2f0000 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <8>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", + "edma2-chan10-rx", "edma2-chan11-tx", + "edma2-chan12-rx", "edma2-chan13-tx", + "edma2-chan14-rx", "edma2-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>; + power-domain-names = "edma2-chan8", "edma2-chan9", + "edma2-chan10", "edma2-chan11", + "edma2-chan12", "edma2-chan13", + "edma2-chan14", "edma2-chan15"; + }; + adma_i2c0: i2c@5a800000 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x5a800000 0x4000>;