From patchwork Mon Aug 7 05:51:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pandey, Radhey Shyam" X-Patchwork-Id: 13343029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA676C04FE2 for ; Mon, 7 Aug 2023 05:53:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230450AbjHGFxT (ORCPT ); Mon, 7 Aug 2023 01:53:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231152AbjHGFxN (ORCPT ); Mon, 7 Aug 2023 01:53:13 -0400 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 897A610F6; Sun, 6 Aug 2023 22:53:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TJxEYtlJaBy6nCPNeHT0lTvf1gDWWe0fQ7GJNXDrcHZUNJPPr6e2JfB3tBhB/R8jZTjQd6LaLtea75YZvT556eR33ewvq97mfAJA+dFL1FLURj6y7nNCd+Ti4kf+pS4sm4YFfGuaKWmElYuhyeJk/nyacMy0uYcyGs7Y1pbyz8El9yF5+AHupvqyaEk3KGsUyEy4l6RIenuzQJ3fFZM1X5eAWs/t+QQ8i0ACQtUhS1c1xMLEGS09qo5+CMR1gLPmIhzT73HOrKyq0krGd9whclIUv7b6Tee8KnkIEKXHSdSdxgGFcTmYAxIgQQ2PU7IdrxNPuouYCYCiwok1SOtbXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bVkuV+hqzWMGKNn2qVg35oaPk+pWRr1972EbPaetRCY=; b=D7ORaN7id/mqfOiGnOsuACHLor9syq7J5rW+nKU79QKRWJVvmLNt1fe0ZDAy1sgJXTsMCKR3pjjI8i9tKAXHA8r+4nI0JKvaY2VW1IkdEX7dmf59JzJJ53Fd4BeH4E5uNs+ojwgFm7r2n7hBtEvGY6Gh+IlSdLtpsA0aVP/3WF70MPAXTPOBYqVMurxU4fZ5Oo2IpoctHIvKHKIwcv1cWwPX/9qOY+rjo9IkHeotlMXP17093Fe0jWRiMkl3IdR5MuYCY6lRXDLqXvggUnHz7XX/mxqYHa7NpMApURW3uPS7l6QGKGiFlcwkKriIldSlkOC7LQ719vnJnK24yfdO2w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bVkuV+hqzWMGKNn2qVg35oaPk+pWRr1972EbPaetRCY=; b=YyIFDYdVnyqhSDttylbPUzsr2uu4jjClru/42epFZjorxl5CgVNIkHdTa63JPrnXpM/xeLhaYXkNCP34tE79NfbrGzpM2NsLhwq+GJnTZbORtRyQTH9/Psv2QYo7k/kUMjMeMHllO6q9gSZHqNcjonJJjTugsqIRtpqCXvW7Gic= Received: from SJ0PR05CA0032.namprd05.prod.outlook.com (2603:10b6:a03:33f::7) by DS0PR12MB8218.namprd12.prod.outlook.com (2603:10b6:8:f2::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6652.26; Mon, 7 Aug 2023 05:53:08 +0000 Received: from CO1PEPF000044F5.namprd05.prod.outlook.com (2603:10b6:a03:33f:cafe::dc) by SJ0PR05CA0032.outlook.office365.com (2603:10b6:a03:33f::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6652.19 via Frontend Transport; Mon, 7 Aug 2023 05:53:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1PEPF000044F5.mail.protection.outlook.com (10.167.241.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6652.19 via Frontend Transport; Mon, 7 Aug 2023 05:53:02 +0000 Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 7 Aug 2023 00:53:01 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Sun, 6 Aug 2023 22:52:50 -0700 Received: from xhdradheys41.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 7 Aug 2023 00:52:46 -0500 From: Radhey Shyam Pandey To: , , , , , , , , , CC: , , , , , , Radhey Shyam Pandey Subject: [PATCH net-next v5 07/10] dmaengine: xilinx_dma: Program interrupt delay timeout Date: Mon, 7 Aug 2023 11:21:46 +0530 Message-ID: <1691387509-2113129-8-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> References: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|DS0PR12MB8218:EE_ X-MS-Office365-Filtering-Correlation-Id: 9c558b65-d473-497b-d684-08db970a901d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rd+gwZCgwjw7Ay2oflc8yU3V5YTx/tvaamwFbFIltpyjbvyumShHBRTeKrK+e2rSV1c0JZm63a+Ih6re3HEg4ML44snFs0oZLUfrfgwe2H7g5fDp+oTMniZ8yvgvDbnwm1f6waoiotwR9c3GdQ662xzcRqEyH0/MnA2RV3hPWYXKF0eFuvnJmyPRM4wzVUmA2bt+Lz+vpOSbCw8REKKC2GsRRN0PGD1AKbV7+Z7U8eNwRb88wzKhVwC34DKayNrBEP8AmysWe4TYYtrwFqu0f96cUiqyXdos7NOjynDw9A99RUO1wm0CgFNRznJess8W7vUJAq6r13AtINsOgpmavrs1NvLSrIeNQWOIuUvvIwohu5CAq7Mb0zhq3cTqwC1719ahvDa1Gu2a7DSGFhpFmWYWGBleLl8VzVkLiG7qDAyaK9LehV74WNPnVFfh9vk3MW3QkLoKHdVxyWtXCATSUBR3Jp3tk5L+Km3EVJv/EvLF3twvrWpZs1TzNJv8EDvOEz5IOFgKzByvzxSHg3BZi36pU/MPotT4e7TrSqoKlQLXTs5W0azoe9hYuJgQftdUr5unRS/yqpunB3wCU27/WAgxTeWSGBUm+DB9Ne5LdjCUpXglsOQF3bRI576teeZl9NmAPhLK0iMYgE4mXpkxb14rcCfcqP8Fy0cGwRUru1i36M6jzRilLznoTUxzISXShPbJt+HHrru53I8sSKP//lfkGTYzZO1LqMSv+ERxz+chcuClahwOmlnOrj4R8+T4Nn9nHo+EOBZHs61QfmR4RzxIdmLJF2WRF/aKVvSKgbIRcAh3dMXuN7Oj99MlU3c4 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(39860400002)(396003)(136003)(82310400008)(186006)(1800799003)(451199021)(40470700004)(46966006)(36840700001)(426003)(41300700001)(26005)(2906002)(5660300002)(83380400001)(7416002)(36860700001)(47076005)(8936002)(8676002)(2616005)(40460700003)(40480700001)(336012)(81166007)(478600001)(86362001)(921005)(316002)(82740400003)(356005)(110136005)(54906003)(70586007)(70206006)(4326008)(966005)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2023 05:53:02.4836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c558b65-d473-497b-d684-08db970a901d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8218 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. It enables dmaengine to respond in real-time even though interrupt coalescing is configured. It also remove the placeholder for delay interrupt and merge it with frame completion interrupt. Since by default interrupt delay timeout is disabled this feature addition has no functional impact on VDMA, MCDMA and CDMA IP's. Signed-off-by: Radhey Shyam Pandey --- Changes for v5: - New patch in this series. Just a note that dmaengine series was earlier sent as separate series[1] and now it's merged with axiethernet series[2]. [1]: https://lore.kernel.org/all/20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com [2]: https://lore.kernel.org/all/20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com - Modified commit description to add "MCDMA" along with VDMA and CDMA IP. - Switch to amd.com email address. --- drivers/dma/xilinx/xilinx_dma.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 6c1c63a38f70..e9f70cad4934 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -173,8 +173,10 @@ #define XILINX_DMA_MAX_TRANS_LEN_MAX 23 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) +#define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) #define XILINX_DMA_CR_COALESCE_SHIFT 16 +#define XILINX_DMA_CR_DELAY_SHIFT 24 #define XILINX_DMA_BD_SOP BIT(27) #define XILINX_DMA_BD_EOP BIT(26) #define XILINX_DMA_BD_COMP_MASK BIT(31) @@ -411,6 +413,7 @@ struct xilinx_dma_tx_descriptor { * @stop_transfer: Differentiate b/w DMA IP's quiesce * @tdest: TDEST value for mcdma * @has_vflip: S2MM vertical flip + * @irq_delay: Interrupt delay timeout */ struct xilinx_dma_chan { struct xilinx_dma_device *xdev; @@ -449,6 +452,7 @@ struct xilinx_dma_chan { int (*stop_transfer)(struct xilinx_dma_chan *chan); u16 tdest; bool has_vflip; + u8 irq_delay; }; /** @@ -1561,6 +1565,9 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) if (chan->has_sg) xilinx_write(chan, XILINX_DMA_REG_CURDESC, head_desc->async_tx.phys); + reg &= ~XILINX_DMA_CR_DELAY_MAX; + reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; + dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); xilinx_dma_start(chan); @@ -1898,15 +1905,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) } } - if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { - /* - * Device takes too long to do the transfer when user requires - * responsiveness. - */ - dev_dbg(chan->dev, "Inter-packet latency too long\n"); - } - - if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { + if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { spin_lock(&chan->lock); xilinx_dma_complete_descriptor(chan); chan->idle = true; @@ -2833,6 +2833,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, /* Retrieve the channel properties from the device tree */ has_dre = of_property_read_bool(node, "xlnx,include-dre"); + of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay); + chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); err = of_property_read_u32(node, "xlnx,datawidth", &value);