[v1,5/5] dmaengine: dw: we do support Merrifield SoC in PCI mode

Commit Message

Andy Shevchenko Sept. 9, 2016, 7:57 p.m. UTC

The Intel Merrifiel SoC contains Intel integrated DMA (iDMA 32-bit) which has
a slightly different register mapping, e.g. some bits in CTL_* and CFG_*
channel registers, and has to use platform data since there is no
autoconfiguration.

The iDMA 32-bit specification is available in the open documentation for Intel
BayTrail SoC as LPE Audio DMA.

Signed-off-by: Andy Shevchenko <[e-mail]>
---
 drivers/dma/dw/pci.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Patch

diff --git a/drivers/dma/dw/pci.c b/drivers/dma/dw/pci.c
index 0ae6c3b..0b14208 100644
--- a/drivers/dma/dw/pci.c
+++ b/drivers/dma/dw/pci.c
@@ -15,6 +15,18 @@ 
 
 #include "internal.h"
 
+static struct dw_dma_platform_data mrfld_pdata = {
+	.nr_channels = 8,
+	.is_private = true,
+	.is_memcpy = true,
+	.is_idma32 = true,
+	.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
+	.chan_priority = CHAN_PRIORITY_ASCENDING,
+	.block_size = 16383,
+	.nr_masters = 1,
+	.data_width = {4},
+};
+
 static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
 {
 	const struct dw_dma_platform_data *pdata = (void *)pid->driver_data;
@@ -103,6 +115,9 @@  static const struct pci_device_id dw_pci_id_table[] = {
 	{ PCI_VDEVICE(INTEL, 0x0f06) },
 	{ PCI_VDEVICE(INTEL, 0x0f40) },
 
+	/* Merrifield iDMA 32-bit (GPDMA) */
+	{ PCI_VDEVICE(INTEL, 0x11a2), (kernel_ulong_t)&mrfld_pdata },
+
 	/* Braswell */
 	{ PCI_VDEVICE(INTEL, 0x2286) },
 	{ PCI_VDEVICE(INTEL, 0x22c0) },