From patchwork Sun Sep 17 14:45:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Br=C3=BCns?= X-Patchwork-Id: 9954833 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 947F060352 for ; Sun, 17 Sep 2017 14:45:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E4A128951 for ; Sun, 17 Sep 2017 14:45:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 718DA28AC8; Sun, 17 Sep 2017 14:45:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7D49E28951 for ; Sun, 17 Sep 2017 14:45:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751302AbdIQOpt (ORCPT ); Sun, 17 Sep 2017 10:45:49 -0400 Received: from mail-out-1.itc.rwth-aachen.de ([134.130.5.46]:18359 "EHLO mail-out-1.itc.rwth-aachen.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750995AbdIQOps (ORCPT ); Sun, 17 Sep 2017 10:45:48 -0400 X-IronPort-AV: E=Sophos;i="5.42,407,1500933600"; d="scan'208";a="13758260" Received: from rwthex-w1-a.rwth-ad.de ([134.130.26.156]) by mail-in-1.itc.rwth-aachen.de with ESMTP; 17 Sep 2017 16:45:47 +0200 Received: from pebbles.fritz.box (77.181.34.79) by rwthex-w1-a.rwth-ad.de (2002:8682:1a9c::8682:1a9c) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1034.26; Sun, 17 Sep 2017 16:45:46 +0200 From: =?UTF-8?q?Stefan=20Br=C3=BCns?= To: CC: Vinod Koul , , "Dan Williams" , =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Kuninori Morimoto Subject: [RFC PATCH] dmaengine: sh: Correct src_addr_widths/dst_addr_widths bitmask setting Date: Sun, 17 Sep 2017 16:45:39 +0200 Message-ID: <20170917144539.3497-1-stefan.bruens@rwth-aachen.de> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 X-Originating-IP: [77.181.34.79] X-ClientProxiedBy: rwthex-s3-a.rwth-ad.de (2002:8682:1aa0::8682:1aa0) To rwthex-w1-a.rwth-ad.de (2002:8682:1a9c::8682:1a9c) Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Obviously, the current value for the burst widths are wrong, and if this value is retrieved from some other subsystem using dma_get_slave_caps, it will wrongly assume burst width of e.g. 3 bytes are supported. Each bit in the bitmask corresponds to a supported width, but it uses an encoding of BIT(), not BIT(log2), as it must be able to encode a width of 3 bytes. The corollary is, it is not possible to encode either a width of 32 or 64 bytes, as the field has a size of 32 bits, and only a subset of the controller capabilities can be exposed. Signed-off-by: Stefan Brüns --- drivers/dma/sh/rcar-dmac.c | 14 ++++++++++---- drivers/dma/sh/shdmac.c | 13 +++++++++---- drivers/dma/sh/usb-dmac.c | 9 ++++++--- 3 files changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c index 2b2c7db3e480..768076caccfd 100644 --- a/drivers/dma/sh/rcar-dmac.c +++ b/drivers/dma/sh/rcar-dmac.c @@ -1734,10 +1734,16 @@ static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac) static int rcar_dmac_probe(struct platform_device *pdev) { - const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE | - DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES | - DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES | - DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES; + /* + * FIXME: Controller supports DMA_SLAVE_BUSWIDTH_32_BYTES + * and DMA_SLAVE_BUSWIDTH_64_BYTES, + * but this overflows the u32 src/dst_addr_widths fields + */ + const u32 widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_16_BYTES); unsigned int channels_offset = 0; struct dma_device *engine; struct rcar_dmac *dmac; diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c index c94ffab0d25c..bf35b5588b11 100644 --- a/drivers/dma/sh/shdmac.c +++ b/drivers/dma/sh/shdmac.c @@ -679,10 +679,15 @@ MODULE_DEVICE_TABLE(of, sh_dmae_of_match); static int sh_dmae_probe(struct platform_device *pdev) { - const enum dma_slave_buswidth widths = - DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES | - DMA_SLAVE_BUSWIDTH_4_BYTES | DMA_SLAVE_BUSWIDTH_8_BYTES | - DMA_SLAVE_BUSWIDTH_16_BYTES | DMA_SLAVE_BUSWIDTH_32_BYTES; + /* + * FIXME: Controller supports DMA_SLAVE_BUSWIDTH_32_BYTES + * but this overflows the u32 src/dst_addr_widths fields + */ + const u32 widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_16_BYTES); const struct sh_dmae_pdata *pdata; unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {}; int chan_irq[SH_DMAE_MAX_CHANNELS]; diff --git a/drivers/dma/sh/usb-dmac.c b/drivers/dma/sh/usb-dmac.c index 31a145154e9f..0ac7e842b70c 100644 --- a/drivers/dma/sh/usb-dmac.c +++ b/drivers/dma/sh/usb-dmac.c @@ -768,7 +768,6 @@ static int usb_dmac_parse_of(struct device *dev, struct usb_dmac *dmac) static int usb_dmac_probe(struct platform_device *pdev) { - const enum dma_slave_buswidth widths = USB_DMAC_SLAVE_BUSWIDTH; struct dma_device *engine; struct usb_dmac *dmac; struct resource *mem; @@ -837,8 +836,12 @@ static int usb_dmac_probe(struct platform_device *pdev) engine->dev = &pdev->dev; - engine->src_addr_widths = widths; - engine->dst_addr_widths = widths; + /* + * FIXME: The controller supports a width of USB_DMAC_SLAVE_BUSWIDTH, + * i.e. 32 bytes, but BIT(32) overflows the u32 bitmask fields. + */ + engine->src_addr_widths = 0; + engine->dst_addr_widths = 0; engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;