From patchwork Sat Jul 21 11:06:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 10538681 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E1DBF602D7 for ; Sat, 21 Jul 2018 11:08:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E8C5E28D65 for ; Sat, 21 Jul 2018 11:08:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DC00328D67; Sat, 21 Jul 2018 11:08:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7F77028D65 for ; Sat, 21 Jul 2018 11:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728287AbeGUMAM (ORCPT ); Sat, 21 Jul 2018 08:00:12 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:44658 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727500AbeGUMAL (ORCPT ); Sat, 21 Jul 2018 08:00:11 -0400 From: Paul Cercueil To: Vinod Koul , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , James Hogan , Zubair Lutfullah Kakakhel Cc: Mathieu Malaterre , Daniel Silsby , Paul Cercueil , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: [PATCH v3 09/18] dmaengine: dma-jz4780: Add support for the JZ4725B SoC Date: Sat, 21 Jul 2018 13:06:34 +0200 Message-Id: <20180721110643.19624-10-paul@crapouillou.net> In-Reply-To: <20180721110643.19624-1-paul@crapouillou.net> References: <20180721110643.19624-1-paul@crapouillou.net> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1532171269; bh=GGigVRljM3YICg0n3wEOEQ+zKhyB1T5rEZF84jaJ9z4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=v553SaQ1ezWW7wYvwITvHsIlP45JFaYurg5PlX00jZgDyQk2nMF+t/8H+fGtLSvKQitNG8VlYFrvh8LVh/0BXWlb3s1Nz9drsW9CP8XsUmodDw7uaOyLwgBShmdEpJVzmrFuIYIHi+oqaem6MyeYPyiJ/wunZ55KnJy1kPdUwJ0= Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The JZ4725B has one DMA core starring six DMA channels. As for the JZ4770, each DMA channel's clock can be enabled with a register write, the difference here being that once started, it is not possible to turn it off. Signed-off-by: Paul Cercueil Tested-by: Mathieu Malaterre Reviewed-by: PrasannaKumar Muralidharan --- drivers/dma/dma-jz4780.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) v2: - Add comments about channel enabling/disabling - The documentation update is now in patch 01/17 v3: No change diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index 084d4023637e..88ce3f0157f6 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c @@ -136,6 +136,7 @@ struct jz4780_dma_chan { enum jz_version { ID_JZ4740, + ID_JZ4725B, ID_JZ4770, ID_JZ4780, }; @@ -209,8 +210,12 @@ static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma, static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, unsigned int chn) { - if (jzdma->version == ID_JZ4770) + if (jzdma->version == ID_JZ4770) { jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn)); + } else if (jzdma->version == ID_JZ4725B) { + /* JZ4725B has no DCKES, it uses DCKE to enable channels */ + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKE, BIT(chn)); + } } static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma, @@ -218,6 +223,8 @@ static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma, { if (jzdma->version == ID_JZ4770) jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn)); + + /* On JZ4725B it is not possible to stop a DMA channel once enabled */ } static struct jz4780_dma_desc *jz4780_dma_desc_alloc( @@ -805,12 +812,14 @@ static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec, static const struct jz4780_dma_soc_data jz4780_dma_soc_data[] = { [ID_JZ4740] = { .nb_channels = 6, .transfer_ord_max = 5, }, + [ID_JZ4725B] = { .nb_channels = 6, .transfer_ord_max = 5, }, [ID_JZ4770] = { .nb_channels = 6, .transfer_ord_max = 6, }, [ID_JZ4780] = { .nb_channels = 32, .transfer_ord_max = 7, }, }; static const struct of_device_id jz4780_dma_dt_match[] = { { .compatible = "ingenic,jz4740-dma", .data = (void *)ID_JZ4740 }, + { .compatible = "ingenic,jz4725b-dma", .data = (void *)ID_JZ4725B }, { .compatible = "ingenic,jz4770-dma", .data = (void *)ID_JZ4770 }, { .compatible = "ingenic,jz4780-dma", .data = (void *)ID_JZ4780 }, {},