From patchwork Wed Jul 25 11:29:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wen He X-Patchwork-Id: 10543877 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E88E1822 for ; Wed, 25 Jul 2018 11:31:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A24829A9F for ; Wed, 25 Jul 2018 11:31:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2C30C29B0E; Wed, 25 Jul 2018 11:31:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C485129A9F for ; Wed, 25 Jul 2018 11:31:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728777AbeGYMnE (ORCPT ); Wed, 25 Jul 2018 08:43:04 -0400 Received: from inva020.nxp.com ([92.121.34.13]:35560 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728690AbeGYMnE (ORCPT ); Wed, 25 Jul 2018 08:43:04 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 42CA11A00E9; Wed, 25 Jul 2018 13:31:47 +0200 (CEST) Received: from smtp.na-rdc02.nxp.com (inv1260.us-phx01.nxp.com [134.27.49.11]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 059561A00D9; Wed, 25 Jul 2018 13:31:47 +0200 (CEST) Received: from az84smr01.freescale.net (az84smr01.freescale.net [10.64.34.197]) by inv1260.na-rdc02.nxp.com (Postfix) with ESMTP id 744BE40C8A; Wed, 25 Jul 2018 04:31:46 -0700 (MST) Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id w6PBVZOF005655; Wed, 25 Jul 2018 04:31:44 -0700 From: Wen He To: vkoul@kernel.org, dmaengine@vger.kernel.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, leoyang.li@nxp.com, jiafei.pan@nxp.com, jiaheng.fan@nxp.com, wen.he_1@nxp.com Subject: [v7 4/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Date: Wed, 25 Jul 2018 19:29:16 +0800 Message-Id: <20180725112919.31340-4-wen.he_1@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180725112919.31340-1-wen.he_1@nxp.com> References: <20180725112919.31340-1-wen.he_1@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document the devicetree bindings for NXP Layerscape qDMA controller which could be found on NXP QorIQ Layerscape SoCs. Signed-off-by: Wen He Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/fsl-qdma.txt | 41 ++++++++++++++++++++ 1 files changed, 41 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt new file mode 100644 index 0000000..99b3d74 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt @@ -0,0 +1,41 @@ +NXP Layerscape SoC qDMA Controller +================================== + +This device follows the generic DMA bindings defined in dma/dma.txt. + +Required properties: + +- compatible: Must be one of + "fsl,ls1021a-qdma": for LS1021A Board + "fsl,ls1043a-qdma": for ls1043A Board + "fsl,ls1046a-qdma": for ls1046A Board +- reg: Should contain the register's base address and length. +- interrupts: Should contain a reference to the interrupt used by this + device. +- interrupt-names: Should contain interrupt names: + "qdma-error": the error interrupt + "qdma-queue": the queue interrupt +- fsl,queues: Should contain number of queues supported. + +Optional properties: + +- dma-channels: Number of DMA channels supported by the controller. +- big-endian: If present registers and hardware scatter/gather descriptors + of the qDMA are implemented in big endian mode, otherwise in little + mode. + +Examples: + + qdma: dma-controller@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8398000 0x0 0x2000 /* Controller registers */ + 0x0 0x839a000 0x0 0x2000>; /* Block registers */ + interrupts = , + ; + interrupt-names = "qdma-error", "qdma-queue"; + dma-channels = <8>; + queues = <2>; + big-endian; + }; + +DMA clients must use the format described in dma/dma.txt file.